MC88915FN55 datasheet, PDF - EEWORLD Datasheet

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MC88915FN55: Description88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28; Categorylogic logic; File Size287KB，13 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MC88915FN55 Overview

88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28

MC88915FN55 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	NXP
Parts packaging code	QLCC
package instruction	QCCJ, LDCC28,.5SQ
Contacts	28
Reach Compliance Code	not_compliant
Other features	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F
series	88915
Input adjustment	MUX
JESD-30 code	S-PQCC-J28
JESD-609 code	e0
length	11.505 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
MaximumI(ol)	0.036 A
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs	1
Number of terminals	28
Actual output times	7
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC28,.5SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	220
power supply	5 V
Certification status	Not Qualified
Same Edge Skew-Max（tskwd）	0.75 ns
Maximum seat height	4.57 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	30
width	11.505 mm
minfmax	55 MHz

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MOTOROLA

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Low Skew CMOS PLL Clock

Driver

The MC88915 Clock Driver utilizes phase–locked loop

technology to lock its low skew outputs’ frequency and phase

onto an input reference clock. It is designed to provide clock

distribution for high performance PC’s and workstations.

The PLL allows the high current, low skew outputs to lock

onto a single clock input and distribute it with essentially zero

delay to multiple components on a board. The PLL also allows

the MC88915 to multiply a low frequency input clock and

distribute it locally at a higher (2X) system frequency. Multiple

88915’s can lock onto a single reference clock, which is ideal

for applications when a central system clock must be

distributed synchronously to multiple boards (see Figure 7).

Five “Q” outputs (QO–Q4) are provided with less than 500

ps skew between their rising edges. The Q5 output is inverted

(180° phase shift) from the “Q” outputs. The 2X_Q output runs

at twice the “Q” output frequency, while the Q/2 runs at 1/2 the

“Q” frequency.

The VCO is designed to run optimally between 20 MHz and

the 2X_Q Fmax specification. The wiring diagrams in Figure 5

detail the different feedback configurations which create

specific input/output frequency relationships. Possible

frequency ratios of the “Q” outputs to the SYNC input are 2:1,

1:1, and 1:2.

The FREQ_SEL pin provides one bit programmable

divide–by in the feedback path of the PLL. It selects between

divide–by–1 and divide–by–2 of the VCO before its signal

reaches the internal clock distribution section of the chip (see

the block diagram on page 2). In most applications

FREQ_SEL should be held high (÷1). If a low frequency

reference clock input is used, holding FREQ_SEL low (÷2) will

allow the VCO to run in its optimal range (>20 MHz).

In normal phase–locked operation the PLL_EN pin is held

high. Pulling the PLL_EN pin low disables the VCO and puts

the 88915 in a static “test mode”. In this mode there is no

frequency limitation on the input clock, which is necessary for

a low frequency board test environment. The second SYNC

input can be used as a test clock input to further simplify

board–level testing (see detailed description on page 11).

A lock indicator output (LOCK) will go high when the loop is

in steady–state phase and frequency lock. The LOCK output

will go low if phase–lock is lost or when the PLL_EN pin is low.

Under certain conditions the lock output may remain low, even

though the part is phase–locked. Therefore the LOCK output

signal should not be used to drive any active circuitry; it should

be used for passive monitoring or evaluation purposes only.

Yield Surface Modeling and YSM are trademarks of Motorola, Inc.

1/97

MC88915

Features

•

Five Outputs (QO–Q4) with Output–Output Skew < 500

ps each being phase and frequency locked to the SYNC

input

•

The phase variation from part–to–part between the SYNC

and FEEDBACK inputs is less than 550 ps (derived from

the tPD specification, which defines the part–to–part

skew)

Freescale Semiconductor, Inc...

•

Input/Output phase–locked frequency ratios of 1:2, 1:1,

and 2:1 are available

•

Input frequency range from 5MHz – 2X_Q FMAX spec

•

Additional outputs available at 2X and +2 the system “Q”

frequency. Also a Q (180° phase shift) output available

•

All outputs have

±36

mA drive (equal high and low) at

CMOS levels, and can drive either CMOS or TTL inputs.

All inputs are TTL–level compatible

•

Test Mode pin (PLL_EN) provided for low frequency

testing. Two selectable CLOCK inputs for test or

redundancy purposes

RST

FEEDBACK

REF_SEL

SYNC[0]

VCC(AN)

RC1

GND(AN)

SYNC[1]

FREQ_SEL

GND

VCC

GND

PLL_EN

VCC

GND

VCC

2X_Q

Q/2

GND

VCC

GND

LOCK

28–Lead Pinout

(Top View)

FN SUFFIX

PLASTIC PLCC

CASE 776–02

ORDERING INFORMATION

MC88915FN55 PLCC

MC88915FN70 PLCC

Motorola, Inc. 1997

For More Information On This Product,

REV 4

Go to: www.freescale.com

MC88915FN55 Related Products

	MC88915FN55	MC88915TFN133R2	MC88915TFN160R2	MC88915TFN55R2	MC88915FN70
Description	88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28	88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28	88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28, PLASTIC, LCC-28	IC,1:8 OUTPUT,CMOS,LDCC,28PIN,PLASTIC	IC,1:8 OUTPUT,CMOS,LDCC,28PIN,PLASTIC
Is it lead-free?	Contains lead	Contains lead	Contains lead	Contains lead	Contains lead
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	QLCC	QLCC	QLCC	QLCC	QLCC
package instruction	QCCJ, LDCC28,.5SQ	QCCJ,	QCCJ,	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ
Contacts	28	28	28	28	28
Reach Compliance Code	not_compliant	not_compliant	not_compliant	not_compliant	not_compliant
Other features	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F	MULTIPLE SELECTABLE FREQUENCY RELATIONS FOR THE CLOCK O/PS; O/P FREQUENCY RATIOS ARE 0.5F/1.0F/2.0F
series	88915	88915	88915	88915	88915
Input adjustment	MUX	MUX	MUX	MUX	MUX
JESD-30 code	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28	S-PQCC-J28
JESD-609 code	e0	e0	e0	e0	e0
length	11.505 mm	11.505 mm	11.505 mm	11.505 mm	11.505 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER	PLL BASED CLOCK DRIVER
Humidity sensitivity level	1	1	1	1	1
Number of functions	1	1	1	1	1
Number of inverted outputs	1	1	1	1	1
Number of terminals	28	28	28	28	28
Actual output times	7	7	7	7	7
Maximum operating temperature	70 °C	85 °C	70 °C	85 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QCCJ	QCCJ	QCCJ	QCCJ
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	220	220	220	220	220
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Same Edge Skew-Max（tskwd）	0.75 ns	0.75 ns	0.75 ns	0.75 ns	0.75 ns
Maximum seat height	4.57 mm	4.57 mm	4.57 mm	4.57 mm	4.57 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	J BEND	J BEND	J BEND	J BEND
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD
Maximum time at peak reflow temperature	30	30	30	30	30
width	11.505 mm	11.505 mm	11.505 mm	11.505 mm	11.505 mm
minfmax	55 MHz	133 MHz	160 MHz	55 MHz	70 MHz
Maker	NXP	NXP	NXP	-	NXP
MaximumI(ol)	0.036 A	-	-	0.036 A	0.036 A
Encapsulate equivalent code	LDCC28,.5SQ	-	-	LDCC28,.5SQ	LDCC28,.5SQ
power supply	5 V	-	-	5 V	5 V
Output characteristics	-	3-STATE	3-STATE	3-STATE	-
Base Number Matches	-	1	1	1	-

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