MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Low Skew CMOS PLL Clock
Driver
The MC88915 Clock Driver utilizes phase–locked loop
technology to lock its low skew outputs’ frequency and phase
onto an input reference clock. It is designed to provide clock
distribution for high performance PC’s and workstations.
The PLL allows the high current, low skew outputs to lock
onto a single clock input and distribute it with essentially zero
delay to multiple components on a board. The PLL also allows
the MC88915 to multiply a low frequency input clock and
distribute it locally at a higher (2X) system frequency. Multiple
88915’s can lock onto a single reference clock, which is ideal
for applications when a central system clock must be
distributed synchronously to multiple boards (see Figure 7).
Five “Q” outputs (QO–Q4) are provided with less than 500
ps skew between their rising edges. The Q5 output is inverted
(180° phase shift) from the “Q” outputs. The 2X_Q output runs
at twice the “Q” output frequency, while the Q/2 runs at 1/2 the
“Q” frequency.
The VCO is designed to run optimally between 20 MHz and
the 2X_Q Fmax specification. The wiring diagrams in Figure 5
detail the different feedback configurations which create
specific input/output frequency relationships. Possible
frequency ratios of the “Q” outputs to the SYNC input are 2:1,
1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable
divide–by in the feedback path of the PLL. It selects between
divide–by–1 and divide–by–2 of the VCO before its signal
reaches the internal clock distribution section of the chip (see
the block diagram on page 2). In most applications
FREQ_SEL should be held high (÷1). If a low frequency
reference clock input is used, holding FREQ_SEL low (÷2) will
allow the VCO to run in its optimal range (>20 MHz).
In normal phase–locked operation the PLL_EN pin is held
high. Pulling the PLL_EN pin low disables the VCO and puts
the 88915 in a static “test mode”. In this mode there is no
frequency limitation on the input clock, which is necessary for
a low frequency board test environment. The second SYNC
input can be used as a test clock input to further simplify
board–level testing (see detailed description on page 11).
A lock indicator output (LOCK) will go high when the loop is
in steady–state phase and frequency lock. The LOCK output
will go low if phase–lock is lost or when the PLL_EN pin is low.
Under certain conditions the lock output may remain low, even
though the part is phase–locked. Therefore the LOCK output
signal should not be used to drive any active circuitry; it should
be used for passive monitoring or evaluation purposes only.
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
1/97
MC88915
Features
•
Five Outputs (QO–Q4) with Output–Output Skew < 500
ps each being phase and frequency locked to the SYNC
input
•
The phase variation from part–to–part between the SYNC
and FEEDBACK inputs is less than 550 ps (derived from
the tPD specification, which defines the part–to–part
skew)
Freescale Semiconductor, Inc...
•
Input/Output phase–locked frequency ratios of 1:2, 1:1,
and 2:1 are available
•
Input frequency range from 5MHz – 2X_Q FMAX spec
•
Additional outputs available at 2X and +2 the system “Q”
frequency. Also a Q (180° phase shift) output available
•
All outputs have
±36
mA drive (equal high and low) at
CMOS levels, and can drive either CMOS or TTL inputs.
All inputs are TTL–level compatible
•
Test Mode pin (PLL_EN) provided for low frequency
testing. Two selectable CLOCK inputs for test or
redundancy purposes
RST
4
FEEDBACK
REF_SEL
SYNC[0]
VCC(AN)
RC1
GND(AN)
SYNC[1]
5
6
7
8
9
10
11
12
FREQ_SEL
13
GND
14
Q0
15
VCC
16
Q1
17
GND
18
PLL_EN
VCC
3
Q5
2
GND
1
Q4
28
VCC
27
2X_Q
26
25
24
23
22
21
20
19
Q/2
GND
Q3
VCC
Q2
GND
LOCK
28–Lead Pinout
(Top View)
FN SUFFIX
PLASTIC PLCC
CASE 776–02
ORDERING INFORMATION
MC88915FN55 PLCC
MC88915FN70 PLCC
©
Motorola, Inc. 1997
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Freescale Semiconductor, Inc.
MC88915
LOCK
FEEDBACK
SYNC (0)
0
SYNC (1)
1
M
U
X
PHASE/FREQ.
DETECTOR
CHARGE PUMP/LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
EXTERNAL REC NETWORK
(RC1 Pin)
REF_SEL
0
1
MUX
D
(÷1)
1
(÷2)
0
D
CP
FREQ_SEL
R
Q
M
U
X
CP
R
2x_Q
Freescale Semiconductor, Inc...
PLL_EN
Q
Q
Q0
DIVIDE
BY TWO
Q1
RST
D
Q
R
Function
Q2
PIN SUMMARY
Pin Name
Num
I/O
CP
SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(0–4)
Q5
2x_Q
Q/2
LOCK
RST
PLL_EN
VCC,GND
1
1
1
1
1
1
5
1
1
1
1
1
1
11
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Input
Input
Reference clock input
Reference clock input
Chooses reference between sync[0] & Sync[1]
Selects Q output frequency
Feedback input to phase detector
Input for external RC network
Clock output (locked to sync)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output(Q) frequency
÷
2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Asynchronous reset (active low)
Disables phase–lock for low freq. testing
Power and ground pins (note pins 8, 10 are
“quiet” supply pins for internal logic only)
D
CP
R
Q
Q3
D
CP
R
Q
Q4
D
CP
R
Q
Q5
D
CP
R
Q
Q/2
MC88915 Block Diagram
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TIMING SOLUTIONS
BR1333 — Rev 6
Freescale Semiconductor, Inc.
MC88915
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND; TA =0° C to + 70° C, VCC = 5.0V
±
5%)
Symbol
VIH
VIL
VOH
VOL
Iin
Parameter
Minimum High–Level Input
Voltage
Maximum Low–Level Input
Voltage
Minimum High–Level Output
Voltage
Maximum Low–Level Output
Voltage
Maximum Input Leakage Current
Maximum ICC/Input
Minimum Dynamic Output Current
3
Test Conditions
Vout = 0.1 V or VCC – 0.1 V
Vout = 0.1 V or VCC – 0.1 V
Vin = VIH or VIL
IOH = –36 mA
1
Vin = VIH or VIL
IOL = 36 mA
1
VI = VCC or GND
VI = VCC – 2.1 V
VOLD = 1.0V Max
VOHD = 3.85 V Max
Maximum Quiescent Supply
Current (per Package)
VI = VCC or GND
VCC
V
4.75
5.25
4.75
5.25
4.75
5.25
4.75
5.25
5.25
5.25
5.25
5.25
5.25
Guaranteed Limit
2.0
2.0
0.8
0.8
4.01
4.51
0.44
0.44
±1.0
1.5
2
88
–88
1.0
Unit
V
V
V
V
µA
mA
mA
mA
mA
Freescale Semiconductor, Inc...
ICCT
IOLD
IOHD
ICC
1.
2.
3.
IOL and IOH are 12mA and –12mA respectively for the LOCK output.
The PLL_EN input pin is not guaranteed to meet this specification.
Maximum test duration is 2.0ms, one output loaded at a time.
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
CIN
CPD
PD1
PD2
Input Capacitance
Power Dissipation Capacitance
Power Dissipation @ 33MHz with 50Ω Thevenin Termination
Power Dissipation @ 33MHz with 50Ω Parallel Termination to GND
Parameter
Typical Values
4.5
40
15 mW/Output
120 mW/Device
37.5 mW/Output
300 mW/Device
Unit
pF
pF
mW
mW
Conditions
VCC = 5.0 V
VCC = 5.0 V
VCC = 5.0 V
T = 25°C
VCC = 5.0 V
T = 25° C
SYNC INPUT TIMING REQUIREMENTS
Symbol
tRISE, tFALL
tCYCLE
Duty Cycle
Parameter
Maximum Rise and Fall times, (SYNC Inputs: From 0.8V – 2.0V)
FN55
Input Clock Period (SYNC Inputs)
36
Input Duty Cycle (SYNC Inputs)
28.5
50%
±25%
Min
–
FN70
Max
3.0
200
1
Unit
ns
ns
1. Information in Fig. 5 and in the “General AC Specification Notes”, Note #3 describes this specification and its actual limits depending on the
application.
FREQUENCY SPECIFICATIONS
(TA =0° C to + 70° C, VCC = 5.0V
±5%,
CL = 50pF)
Guaranteed Minimum
Symbol
fmax
1
Parameter
Maximum Operating Frequency (2X_Q Output)
Maximum Operating Frequency (Q0–Q4,Q5 Output)
MC88915FN55
55
27.5
MC88915FN70
70
35
Unit
MHz
MHz
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded at 50 pF.
TIMING SOLUTIONS
BR1333 — Rev 6
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MOTOROLA
Freescale Semiconductor, Inc.
MC88915
AC ELECTRICAL CHARACTERISTICS
(TA =0° C to +70° C, VCC = 5.0V
±5%,
CL = 50pF)
Symbol
tRISE, tFALL
(Outputs)
tRISE, tFALL
3
(2X_Q Output)
tPulse Width
3
(Q0,Q1,Q3,Q4,
Q5,Q/2)
Parameter
Rise and Fall Times, all Outputs Into a 50 pF, 500
Ω
Load
(Between 0.2VCC and 0.8VCC)
Rise and Fall Time, 2X_Q Output Into a 20 pF Load With Termina-
tion specified in note 2 (Between 0.8 V and 2.0 V)
Output Pulse Width (Q0, Q1, Q3, Q4, Q5, Q/2 @VCC/2)
Min
1.0
0.5
0.5tCYCLE – 0.5
Max
2.5
1.6
0.5tCYCLE + 0.5
Unit
ns
ns
tCYCLE = 1/Freq. at which the “Q”
Outputs are running
ns
tPulse Width
3
(Q2 only)
Output Pulse Width (Q2 Output @ VCC/2)
Output Pulse Width (2X_Q Output @ 1.5 V) (See AC Note 2)
Output Pulse Width (2X_Q Output @ VCC/2)
0.5tCYCLE – 0.6
0.5tCYCLE – 0.5
0.5tCYCLE – 1.0
0.5tCYCLE + 0.6
0.5tCYCLE + 0.5
0.5tCYCLE + 1.0
ns
ns
Freescale Semiconductor, Inc...
tPulse Width
3
(2X_Q Output)
tPulse Width
3
(2X_Q Output)
tPD
3
(Sync–Feedback)
(470kΩ From RC1 to An.VCC)
SYNC input to feedback delay
(meas. @ SYNC0 or 1 and FEEDBACK input pins)
(See General AC Specification note 4 and Fig. 2 for explanation)
–1.05
–0.50
ns
(470kΩ From RC1 to An.GND)
+1.25
–
–
–
1
1.5
+3.25
500
750
750
10
13.5
tSKEWr
1,3
(Rising)
tSKEWf
1,3
(Falling)
tSKEWall
1,3
tLOCK
tPHL
(Reset – Q)
Output–to–Output Skew Between Outputs Q0 – Q4, Q/2
(Rising Edges Only)
Output–to–Output Skew Between Outputs Q0 – Q4
(Falling Edges Only)
Output–to–Output Skew Between Outputs 2X_Q, Q/2, Q0 – Q4
Rising, Q5 Falling
Time Required to acquire
2
Phase–Lock from time SYNC Input Sig-
nal is Received.
Propagation Delay, RST to Any Output (High–Low)
ps
ps
ps
ms
ns
1. Under equally loaded conditions, CL
≤50pF
(±2pF), and at a fixed temperature and voltage.
2. With VCC fully powered–on and an output properly connected to the FEEDBACK pin. tLOCK Max. is with C1 = 0.1µF, tLOCK Min is with
C1 = 0.01µF.
3. These specifications are not tested, they are guaranteed by statistical characterization. See General AC Specification note 1.
RESET TIMING REQUIREMENTS
1
Symbol
tREC, RST
to SYNC
tW, RST
LOW
Parameter
Reset Recovery Time rising RST
edge to falling SYNC edge
Minimum Pulse Width,
RST input LOW
Minimum
9.0
5.0
Unit
ns
ns
1. These reset specs are valid only when PLL_EN is LOW and the part is in Test mode (not in phase–lock)
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TIMING SOLUTIONS
BR1333 — Rev 6
Freescale Semiconductor, Inc.
MC88915
General AC Specification Notes
1. Several specifications can only be measured when the
MC88915 is in phase–locked operation. It is not possible
to have the part in phase–lock on ATE (automated test
equipment). Statistical characterization techniques were
used to guarantee those specifications which cannot be
measured on the ATE. MC88915 units were fabricated
with key transistor properties intentionally varied to
create a 14 cell designed experimental matrix. IC
performance was characterized over a range of transistor
properties (represented by the 14 cells) in excess of the
expected process variation of the wafer fabrication area.
Response Surface Modeling (RSM) techniques were
used to relate IC performance to the CMOS transistor
properties over operation voltage and temperature. IC
Performance to each specification and fab variation were
used in conjunction with Yield Surface Modeling™ (YSM
™)
methodology to set performance limits of ATE testable
specifications within those which are to be guaranteed by
statistical characterization. In this way all units passing
the ATE test will meet or exceed the non–tested
specifications limits.
2. These two specs (tRlSE/FALL and tPULSE Width 2X_Q
output) guarantee that the MC88915 meets the 25 MHz
68040 P–Clock input specification (at 50 MHz). For these
two specs to be guaranteed by Motorola, the termination
scheme shown below in Figure 1 must be used.
3. The wiring Diagrams and written explanations in Figure 5
demonstrate the input and output frequency relationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5 output, thus creating a
180° phase shift between the SYNC input and the “Q”
outputs. Table 1 below summarizes the allowable SYNC
frequency range for each possible configuration.
Freescale Semiconductor, Inc...
88915
2X_Q
Output
Rs
ZO (CLOCK TRACE)
68040
P–Clock
Input
Rs = Zo – 7
Ω
Rp
Rp = 1.5 Zo
Figure 1. MC68040 P–Clock Input Termination Scheme
FREQ_SEL
Level
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Feedback
Output
Q/2
Any “Q” (Q0–Q4)
Q5
2X_Q
Q/2
Any “Q” (Q0–Q4)
Q5
2X_Q
Allowable SYNC Input
Frequency Range (MHZ)
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
2.5 to (2X_Q FMAX Spec)/8
5 to (2X_Q FMAX Spec)/4
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
Corresponding VCO
Frequency Range
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAXSpec)
20 to (2X_Q FMAXSpec)
Phase Relationships
of the “Q” Outputs
to Rising SYNC Edge
0°
0°
180°
0°
0°
0°
180°
0°
Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations.
4. A 1 MΩ resistor tied to either Analog VCC or Analog GND
as shown in Figure 2 is required to ensure no jitter is
present on the MC88915 outputs. This technique causes
a phase offset between the SYNC input and the output
connected to the FEEDBACK input, measured at the
input pins. The tPD spec describes how this offset varies
with process, temperature, and voltage. The specs were
arrived at by measuring the phase relationship for the 14
lots described in note 1 while the part was in
phase–locked operation. The actual measurements were
made with a 10 MHz SYNC input (1.0 ns edge rate from
0.8 V – 2.0 V) with the Q/2 output fed back. The phase
measurements were made at 1.5 V. The Q/2 output was
terminated at the FEEDBACK input with 100Ω to VCC and
100
Ω
to ground.
TIMING SOLUTIONS
BR1333 — Rev 6
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