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CD4044BFMSR

Description
4000/14000/40000 SERIES, LOW LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16
Categorylogic    logic   
File Size109KB,10 Pages
ManufacturerRenesas Electronics Corporation
Websitehttps://www.renesas.com/
Download Datasheet Parametric Compare View All

CD4044BFMSR Overview

4000/14000/40000 SERIES, LOW LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16

CD4044BFMSR Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerRenesas Electronics Corporation
Parts packaging codeDIP
package instructionFRIT SEALED, CERAMIC, DIP-16
Contacts16
Reach Compliance Codenot_compliant
series4000/14000/40000
JESD-30 codeR-GDIP-T16
JESD-609 codee0
Load capacitance (CL)50 pF
Logic integrated circuit typeR-S LATCH
MaximumI(ol)0.00036 A
Number of digits4
Number of functions1
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output characteristics3-STATE
Output polarityTRUE
Package body materialCERAMIC, GLASS-SEALED
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5/15 V
Prop。Delay @ Nom-Sup405 ns
propagation delay (tpd)405 ns
Certification statusNot Qualified
Filter levelMIL-PRF-38535 Class V
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)18 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
total dose100k Rad(Si) V
Trigger typeLOW LEVEL
width7.62 mm
CD4043BMS
CD4044BMS
December 1992
CMOS Quad 3 State R/S Latches
Pinout
CD4043BMS
TOP VIEW
Features
• High Voltage Types (20V Rating)
• Quad NOR R/S Latch- CD4043BMS
• Quad NAND R/S Latch - CD4044BMS
• 3 State Outputs with Common Output ENABLE
• Separate SET and RESET Inputs for Each Latch
• NOR and NAND Configuration
• 5V, 10V and 15V Parametric Ratings
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µa at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25
o
C
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of ‘B’
Series CMOS Devices”
Q4 1
Q1 2
R1 3
S1 4
ENABLE 5
S2 6
R2 7
VSS 8
16 VDD
15 R4
14 S4
13 NC
12 S3
11 R3
10 Q3
9 Q2
NC = NO CONNECTION
CD4044BMS
TOP VIEW
Q4 1
NC 2
S1 3
R1 4
ENABLE 5
R2 6
S2 7
VSS 8
16 VDD
15 S4
14 R4
13 Q1
12 R3
11 S3
10 Q3
9 Q2
Applications
• Holding Register in Multi-Register System
• Four Bits of Independent Storage with Output ENABLE
• Strobed Register
• General Digital Logic
• CD4043BMS for Positive Logic Systems
• CD4044BMS for Negative Logic Systems
NC = NO CONNECTION
Description
CD4043BMS types are quad cross-coupled 3-state CMOS NOR
latches and the CD4044BMS types are quad cross-coupled 3-
state CMOS NAND latches. Each latch has a separate Q output
and individual SET and RESET inputs. The Q outputs are con-
trolled by a common ENABLE input. A logic “1” or high on the
ENABLE input connects the latch states to the Q outputs. A logic
“0” or low on the ENABLE input disconnects the latch states from
the Q outputs, results in an open circuit feature allows common
busing of the outputs.
The CD4043BMS and CD4044BMS are supplied in these 16-
lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
*CD4043B Only
*H4T
†H4T
*H1C
†HIE
*H3X †H6W
†CD4044B Only
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3311
7-876

CD4044BFMSR Related Products

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Description 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDFP16, CERAMIC, FP-16 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDIP16, SIDE BRAZED, CERAMIC, DIP-16 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDFP16, CERAMIC, DFP-16 4000/14000/40000 SERIES, HIGH LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16
Parts packaging code DIP DFP DIP DIP DFP DIP
package instruction FRIT SEALED, CERAMIC, DIP-16 DFP, FL16,.3 DIP, DIP16,.3 DIP, DIP16,.3 DFP, FL16,.3 FRIT SEALED, CERAMIC, DIP-16
Contacts 16 16 16 16 16 16
Reach Compliance Code not_compliant compliant compliant not_compliant not_compliant not_compliant
series 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000 4000/14000/40000
JESD-30 code R-GDIP-T16 R-CDFP-F16 R-CDIP-T16 R-CDIP-T16 R-CDFP-F16 R-GDIP-T16
JESD-609 code e0 e4 e4 e0 e0 e0
Load capacitance (CL) 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type R-S LATCH R-S LATCH R-S LATCH R-S LATCH R-S LATCH R-S LATCH
MaximumI(ol) 0.00036 A 0.00064 A 0.00064 A 0.00036 A 0.00036 A 0.00036 A
Number of digits 4 4 4 4 4 4
Number of functions 1 1 1 1 1 1
Number of terminals 16 16 16 16 16 16
Maximum operating temperature 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
Minimum operating temperature -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Output polarity TRUE TRUE TRUE TRUE TRUE TRUE
Package body material CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED
encapsulated code DIP DFP DIP DIP DFP DIP
Encapsulate equivalent code DIP16,.3 FL16,.3 DIP16,.3 DIP16,.3 FL16,.3 DIP16,.3
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form IN-LINE FLATPACK IN-LINE IN-LINE FLATPACK IN-LINE
power supply 5/15 V 5/15 V 5/15 V 5/15 V 5/15 V 5/15 V
Prop。Delay @ Nom-Sup 405 ns 405 ns 405 ns 405 ns 405 ns 405 ns
propagation delay (tpd) 405 ns 405 ns 405 ns 405 ns 405 ns 405 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Filter level MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
Maximum seat height 5.08 mm 2.92 mm 5.08 mm 5.08 mm 2.92 mm 5.08 mm
Maximum supply voltage (Vsup) 18 V 18 V 18 V 18 V 18 V 18 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V 3 V 3 V 3 V
Nominal supply voltage (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V
surface mount NO YES NO NO YES NO
technology CMOS CMOS CMOS CMOS CMOS CMOS
Temperature level MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
Terminal surface Tin/Lead (Sn/Pb) GOLD GOLD Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE FLAT THROUGH-HOLE THROUGH-HOLE FLAT THROUGH-HOLE
Terminal pitch 2.54 mm 1.27 mm 2.54 mm 2.54 mm 1.27 mm 2.54 mm
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL
total dose 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V 100k Rad(Si) V
Trigger type LOW LEVEL HIGH LEVEL HIGH LEVEL LOW LEVEL LOW LEVEL HIGH LEVEL
width 7.62 mm 6.73 mm 7.62 mm 7.62 mm 6.73 mm 7.62 mm
Is it Rohs certified? incompatible - - incompatible incompatible incompatible
Peak Reflow Temperature (Celsius) NOT SPECIFIED - - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Maximum time at peak reflow temperature NOT SPECIFIED - - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Base Number Matches - 1 1 1 1 -

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