Standard SRAM, 256KX16, 85ns, CMOS, PBGA48, 7 X 8.50 MM, 1.10 MM HEIGHT, FINE PITCH, TBGA-48
CY62147V18-85BAI Parametric
Parameter Name
Attribute value
Is it lead-free?
Contains lead
Is it Rohs certified?
incompatible
Maker
Cypress Semiconductor
Parts packaging code
BGA
package instruction
7 X 8.50 MM, 1.10 MM HEIGHT, FINE PITCH, TBGA-48
Contacts
48
Reach Compliance Code
compliant
ECCN code
3A991.B.2.A
Maximum access time
85 ns
I/O type
COMMON
JESD-30 code
R-PBGA-B48
JESD-609 code
e0
length
8.5 mm
memory density
4194304 bit
Memory IC Type
STANDARD SRAM
memory width
16
Number of functions
1
Number of terminals
48
word count
262144 words
character code
256000
Operating mode
ASYNCHRONOUS
Maximum operating temperature
85 °C
Minimum operating temperature
-40 °C
organize
256KX16
Output characteristics
3-STATE
Package body material
PLASTIC/EPOXY
encapsulated code
TFBGA
Encapsulate equivalent code
BGA48,6X8,30
Package shape
RECTANGULAR
Package form
GRID ARRAY, THIN PROFILE, FINE PITCH
Parallel/Serial
PARALLEL
Peak Reflow Temperature (Celsius)
240
power supply
1.8 V
Certification status
Not Qualified
Maximum seat height
1.2 mm
Maximum standby current
0.000025 A
Minimum standby current
1 V
Maximum slew rate
0.007 mA
Maximum supply voltage (Vsup)
1.95 V
Minimum supply voltage (Vsup)
1.75 V
Nominal supply voltage (Vsup)
1.8 V
surface mount
YES
technology
CMOS
Temperature level
INDUSTRIAL
Terminal surface
Tin/Lead (Sn/Pb)
Terminal form
BALL
Terminal pitch
0.75 mm
Terminal location
BOTTOM
Maximum time at peak reflow temperature
30
width
7 mm
CY62147V18-85BAI Preview
CY62147V18 MoBL2™
256K x 16 Static RAM
Features
• Low voltage range:
— CY62147V18: 1.75V–1.95V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
BHE are HIGH. The input/output pins (I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
17
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
17
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62147V18 is available in 48-ball FBGA packaging.
Functional Description
The CY62147V18 is a high-performance CMOS static RAM
organized as 262,144 words by 16 bits. These devices feature
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL™) in por-
table applications such as cellular telephones. The devices
also have an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH) or when CE is LOW and both BLE and
Logic Block Diagram
DATA IN DRIVERS
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
256K x 16
RAM Array
2048 x 2048
SENSE AMPS
I/O
0
– I/O
7
I/O
8
– I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
BHE
BLE
Pow
-
er Down
Circuit
MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 6, 2000
CY62147V18 MoBL2™
Pin Configuration
FBGA
1
BLE
I/O
8
I/O
9
V
SS
V
CC
I/O
14
I/O
15
NC
2
OE
BHE
I/O
10
I/O
11
I/O
12
I/O
13
NC
A
8
Top View
4
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
NC
I/O
0
I/O
2
V
CC
V
SS
I/O
6
I/O
7
NC
A
B
C
D
E
F
G
H
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied ............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +2.4V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................... −0.5V
to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Device
Range
Ambient
Temperature
V
CC
CY62147V18 Industrial
–40°C to +85°C 1.75V to 1.95V
Product Portfolio
Power Dissipation (Industrial)
V
CC
Range
Product
CY62147V18
V
CC(min.)
V
CC(typ.)
[2]
V
CC(max.)
1.75V
1.8V
1.95V
Power
Std.
Operating (I
CC
)
Typ.
[2]
3 mA
Maximum
7 mA
Typ.
[2]
20
µA
Standby (I
SB2
)
Maximum
50
µA
Notes:
1. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ.)
, T
A
= 25°C.
2
CY62147V18 MoBL2™
Electrical Characteristics
Over the Operating Range
CY62147V18
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
V
CC
Operating Supply
Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
,
CMOS Levels
V
CC
= 1.95V
Test Conditions
I
OH
= –0.1 mA
I
OL
= 0.1 mA
V
CC
= 1.75V
V
CC
= 1.75V
V
CC
= 1.95V
V
CC
= 1.75V
1.4
–0.5
–1
–1
±1
+1
3
Min.
1.5
0.2
V
CC
+ 0.3V
0.4
+1
+1
7
Typ.
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
I
OUT
= 0 mA, f = 1 MHz,
CMOS Levels
I
SB1
Automatic CE
Power-Down Current—
CMOS Inputs
Automatic CE
Power-Down Current—
CMOS Inputs
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V, f = f
MAX
CE > V
CC
– 0.3V
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V, f = 0
V
CC
=
1.95V
Std.
1
2
100
mA
µA
I
SB2
20
50
µA
.
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ.)
Max.
6
8
Unit
pF
pF
Thermal Resistance
Description
Thermal Resistance
(Junction to Ambient)
[3]
Thermal Resistance
(Junction to Case)
[3]
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Test Conditions
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed
circuit board
Symbol
Θ
JA
Θ
JC
BGA
55
16
Units
°C/W
°C/W
3
CY62147V18 MoBL2™
AC Test Loads and Waveforms
R1
V
CC
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
R1
V
CC
Typ
10%
GND
Rise TIme: 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time: 1 V/ns
(a)
(b)
(C)
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
V
TH
OUTPUT
Parameters
R1
R2
R
TH
V
TH
.
1.8V
15294
11300
6500
0.85V
Unit
Ohms
Ohms
Ohms
Volts
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.0V
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V
No input may exceed
V
CC
+ 0.3V
Std.
Conditions
Min.
1.0
10
Typ.
[2]
Max.
1.95
25
Unit
V
µA
t
CDR[3]
t
R[4]
Chip Deselect to Data
Retention Time
Operation Recovery Time
0
85
ns
ns
Note:
4. Full Device AC operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 10
µs
or stable at V
CC(min.)
>10
µs.
Data Retention Waveform
DATA RETENTION MODE
V
CC
V
CC(min)
t
CDR
V
DR
> 1.0 V
V
CC(min)
t
R
CE
4
CY62147V18 MoBL2™
Switching Characteristics
Over the Operating Range
[5]
85 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE[7]
t
HZBE
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
[9, 10]
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6, 8]
OE HIGH to High Z
[8]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 8]
CE LOW to Power-Up
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BHE / BLE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[6, 8]
WE HIGH to Low Z
[6]
Min.
85
Max.
Unit
ns
85
10
85
45
5
25
10
25
0
85
85
5
25
85
75
75
0
0
65
75
45
0
35
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V
CC(typ.)
, and output loading of the
specified I
OL
/I
OH
and 30 pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. If both byte enables are toggled together this value is 10ns
8. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t
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