device manufactured using Numonyx’s 0.15um process
containing 134,217,728 bits organized as either 16,777,218 (x8)
technology. This
(x16). The device is uniformly sectored with
or 8,388,608 bytes
device containing 134,217,728 bits organized
as
hundred and twenty eight 128KB ERASE blocks.
one
either 16,777,218 (x8) or 8,388,608 bytes (x16). The device
is uniformly sectored with one hundred and twenty eight 128KB
ERASE blocks.
AS28F128J3MRG
Revision 5.0 11/23/04
This device features in-system
block
locking. They also have
This device features in-system
block
locking. They also have
a
Common FLASH Interface [CFI] that permits software algorithms
a Common FLASH Interface [CFI] that permits software
to be used for entire families of devices. The software is device-
algorithms to be used for entire families of devices. The
independent, JEDEC ID-independent with forward and backward
software is device-independent, JEDEC ID-independent with
compatibility.
forward and backward compatibility.
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at
www.austinsemiconductor.com
AS28F128J3A
Rev. 5.8 8/13
1
Micross Components reserves the right to change products or specifications without notice.
1
Austin Semiconductor, Inc.
Functional Block Diagram:
AS28F128J3A
Q-Flash
Q-Flash
Input
Buffer
PEM
PEM
AS28F128J3M
I/O
CNTL
Logic
ADDR
Buffer/
Latch
128KB Memory Block (0)
128KB Memory Block (1)
128KB Memory Block (2)
128KB Memory Block (3)
X
Decode
ADDR.
Counter
Block
Erase
Control
Power
(Current)
Control
Bus
Configuration
Register [BCR]
WRITE
Buffer
CEx
OE\
WE\
RP\
WP\
CLK
STS
VPEN
WAIT
VPP
Switch
Pump
Sense Amplifiers
WRITE/ERASE Bit
Compare and
Verify
Command
Execution
Logic
[CEL]
ISM
Y
Dec.
128KB Memory Block (n)
DQ0-8 or
DQ0-15
Y - Select
Control
Status
Register
Identification
Register
Query
Output
Buffer
Additionally, the Scaleable Command Set [SCS]
work with all SCS
VPEN serves as
as an input with 2.7V, 3.3V or 5V levels for
simple software driver in all host systems to
allows a single,
VPEN serves
an input with 2.7V, 3.3V or 5V levels for
simple software driver in all host systems to work with all SCS application programming. VPEN
in this Q-Flash device can
compliant FLASH memory devices. The SCS provides the fastest application programming. VPEN
in this Q-Flash device can
system/device data transfer rates and minimizes the device
provide data protection when connected
ground. This pin
compliant FLASH memory devices. The SCS provides the
and
provide data protection when connected to
ground. This pin also
system-level implementation costs.
enables PROGRAM or
or ERASE LOCKOUT functions/
fastest system/device data transfer rates and minimizes the also enables PROGRAM
ERASE LOCKOUT functions/controls
during power
power transitions.
device and system-level implementation costs.
controls during
transitions.
Additionally, the Scaleable Command Set [SCS] allows a single,
To optimize the processor-memory interface, the device
accommodates VPEN, which is switchable during BLOCK This device is an even-sectored device architecture offering
To
ERASE, PROGRAM, or LOCK BIT configurations and in
This device
BLOCK LOCKING that can
architecture
UN-LOCK a
optimize the processor-memory interface, the device
is an even-sectored device
LOCK and
offering
individual
accommodates
be hard-wired to VCC all dependent
BLOCK
end
individual BLOCK LOCKING that can LOCK and UN-LOCK
addition can
VPEN, which is switchable during
on the
block using the SECTOR LOCK BITS command sequence.
ERASE, PROGRAM, or
is treated as
configurations and
enable
a block using the SECTOR LOCK BITS command sequence.
LOCK BIT
an input pin to
in
application(s). VPEN
addition can be hard-wired to VCC all dependent on the end
ERASING, PROGRAMMING, and BLOCK LOCKING. When Status [STS] is a logic signal output that gives an additional
VPEN is lower than the VCC lockout voltage (VLKO),
indicator of
is logic
state
output
[ISM] activity by providing
application(s). VPEN is treated as an input pin to enable
all
Status [STS]
the
a
internal
signal
machine
that gives an additional
program functions are disabled.
and BLOCK LOCKING. indicator of the internal state
status and
[ISM]
masking.
by
BLOCK ERASE SUSPEND a hardware signal of both the
machine
status
activity
This
ERASING, PROGRAMMING,
mode enables the
than the VCC lockout
ERASE to READ data status indicator minimizes central processing unit overhead
When VPEN is lower
user to stop BLOCK
voltage (VLKO), all providing a hardware signal of both the status and status
and
from
functions are disabled.
any other blocks. Similarly, system
This
consumption. In the default mode,
processing
program
or PROGRAM data to
BLOCK ERASE SUSPEND masking.
power
status indicator minimizes central
STS acts as an
PROGRAM
RY/BY\ pin.
mode enables
SUSPEND mode
BLOCK
the user to SUSPEND
unit overhead and
When LOW, STS indicates that the ISM is
the user to stop
enables
ERASE to READ
system power consumption. In the default
PROGRAMMING to READ data or execute code from any un- performing a BLOCK ERASE, PROGRAM, or LOCK BIT
data from or
block(s).
suspended
PROGRAM data to any other blocks. Similarly, mode, STS acts as an RY/BY\ pin. When LOW, STS
ISM is ready
configuration. When HIGH, STS indicates that the
indicates
PROGRAM SUSPEND mode enables the user to SUSPEND that the
new command.
for a
ISM is performing a BLOCK ERASE, PROGRAM,
PROGRAMMING to READ data or execute code from any
or LOCK BIT configuration. When HIGH, STS indicates that
AS28F128J3MRG
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
un-suspended
11/23/04
block(s).
the ISM is ready for a new command.
Revision 5.0
For Additional Products and Information visit out Web site at
www.austinsemiconductor.com
2
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
2
AS28F128J3A
Q-Flash
Three Chip Enable (CEx) pins are used for enabling and
disabling the device by activating the device’s control logic,
input buffer, decoders, and sense amplifiers.
BYTE\ enables the device to be used in x8 or x16 configuration.
Byte=Low (logic 0) selects and 8-bit mode with address zero
(A0) selecting the High or Low Byte and Byte=High (logic 1)
selects the 16-bit or Word mode. When the device is in Word
mode, address one (A1) becomes the low order address bit and
address zero (A0) becomes a no-connect (NC).
RP\ is used to reset the device. When the device is disabled
and RP\ is at VCC, the STANDBY mode is enabled. A reset
time (tRWH) is required after RP\ switches to a High (logic 1)
and the outputs become valid. Likewise, the device has a wake
time (tRS) from RP\ High until WRITES to the Command User
Interface [CUI] are recognized, RESETS the ISM and clears
the status register.
PEM
Chip Enable Truth Table
CE2
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
CE1
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
CE0
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
Device
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
Capacitance
Absolute Maximum Ratings
Voltage
Temperature Under Bias
Storage Temperature
Short Circuit Current
Min
‐55
‐65
Max
125
125
100
Units
o
C
o
C
mA
Notes
Symbol
Typ
Max
Units
Cin
5
8
pF
Cbyte
14
16
pF
Output Capacitance
Cout
5
12
pF
Stress greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any
other conditions greater than those indicated in the operational sec-
tions of this specification is not implied. Exposure to absolute maximum
conditions for any duration or segment of time may affect device
reliability.
Parameter/Condition
Input Capacitance
1
Notes
1: All specified voltages are with respect to GND. Minimum DC
voltage is -0.5v on input/output pins and -0.2v on Vcc and VPEN
pins. During transitions, this level may undershoot to -2.0v for
periods </= 20ns. Maximum DC voltage on input/output pins,
Vcc and VPEN is VCC+0.5V which, during transitions, may
overshoot to Vcc + 2.0v for periods <20ns.
Pin Description Table
Signal Name
Symbol
A0, A1, A2, A3, A4,
A5, A6, A7, A8, A9,
A10, A11,
A12,A13,A14,A15,
A16,A17,A18,A19,
A20,A21,A22,A23
CE0, CE1, CE2
WE\
RP\
OE\
BYTE\
VPEN
Type
Pin
32,28,27,26,
25,24,23,22,
20,19,18,17,
13,12,11,10,
8,7,6,5,
4,3,1,30
14, 2, 29
55
16
54
31
15
Description
Address Inputs during READ and WRITE Operations. A0 is only used in x8
mode and will be a NC in x16 mode.
Address
Input
Chip Enables
Write Enable
Reset/Power Down
Output Enable
Byte Mode Control
Programming Voltage
Input
Input
Input
Input
Input
Input
Status Pin/Flag
Input/Output Voltage
Supply Voltage
Digital Ground
No Connect(s)
STS
VCCQ
VCC
GND
NC
Output
Supply
Supply
Supply
‐
53
43
9, 37
21,42,48
1,30,56
Three Chip Enable pins for Multiple devices. See chart for function
Write Control
Reset/Power‐Down, When Low the control pin resets the status Reg.and
ISM to array READ mode.
Output Enable control enable data output buffers when Low, and when
High the output buffers are disabled
Configuration Control pin. When High the device is in x16 mode, when
Low the device is in Byte mode (x8)
Necessary Voltage pin for Programming, Erasing or configuring lock bits.
Typically connected to VCC. When VPEN</=VPENLK, this
enables Hardware Write Protect.
Indicates the status of the ISM. When configured in level mode, STS acts
as a RY/BY\ pin. When configured in its pulse mode, it can
pulse to indicate PROGRAM and or ERASE completion.
Separate/Isolated Voltage supply for Input/Output bus. Allows
voltage matching to different interface standards.
Power Supply: 2.7V‐3.6V
Ground
No electrical connection or function
Micross Components reserves the right to change products or specifications without notice.
AS28F128J3A
Rev. 5.8 8/13
3
AS28F128J3A
Q-Flash
Bus Operations
Mode
Read Array
Output Disable
Standby
Reset/Power‐Down
Read Identifier Codes
Read Query
Read Status (ISM off)
Read Status (ISM on)
Write
RP\
VIH
VIH
VIH
VIL
VIH
VIH
VIH
VIH
VIH
CE0
Enabled
Enabled
Disabled
X
Enabled
Enabled
Enabled
Enabled
Enabled
CE1
Enabled
Enabled
Disabled
X
Enabled
Enabled
Enabled
Enabled
Enabled
CE2
Enabled
Enabled
Disabled
X
Enabled
Enabled
Enabled
Enabled
Enabled
OE\
VIL
VIH
X
X
VIL
VIL
VIL
VIL
VIH
WE\
VIH
VHI
X
X
VIH
VIH
VIH
VIH
VIL
VPEN
X
X
X
X
X
X
X
X
VPENH
DQ
Dout
High‐Z
High‐Z
High‐Z
Notes
1,2,3
Address
X
X
X
X
See Table 31 of Numonyx DS
See CFI Query of Numonyx DS
X
X
X
STS Default Mode
High‐Z (VOH with External PU)
X
X
High‐Z (VOH with External PU)
High‐Z (VOH with External PU)
High‐Z (VOH with External PU)
X
X
X
PEM
4
5
Dout
Din
3,6,7
Notes
1 Refer to DC Characteristics. When VPEN</= VPENLK, memory contents can be read but not altered
2 X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and VPENH voltages
3 In default mode, STA is VOL when the ISM is executing internal Block Erase, Program, or lock bit configuration algorithms. It is VOH when the ISM is not busy, in block erase suspend
mode, program suspend mode, or reset/power-down mode.
4 See Read Identifier codes of the Numonyx Datasheet (DS)
5 See Read Query Mode Command section of the Numonyx Datasheet (DS)
6 Command Writes involving block erase, program, or lock bit configuration are reliably executed when VPEN=VPENH and VCC is within Specification
7 Refer to Table 19 on page 35 of the Numonyx Datasheet (DS)
DC Electrical Characteristics
V
CCQ
Symbol
I
LI
I
LO
V
CC
Parameter
Input and V
PEN
Load Current
Output Leakage Current
(TA=Min/Max temperatures of Operational Range chosen)
2.7 ‐ 3.6V
Typ
‐
‐
2.7 ‐ 3.6V
Max
±1
±10
Units
µA
µA
Test Conditions
V
CC
= V
CC
Max; V
CCQ
= V
CCQ
Max
V
IN
= V
CCQ
or V
SS
V
CC
= V
CC
Max; V
CCQ
= V
CCQ
Max
V
IN
= V
CCQ
or V
SS
CMOS Inputs, V
CC
= V
CC
Max; V
CCQ
=
V
CCQ
Max, Device is disabled,
RP# = V
CCQ
± 0.2 V
TTL Inputs, V
CC
= V
CC
Max,
V
CCQ
= V
CCQ
Max, Device is disabled, RP# = V
IH
RP# = V
SS
± 0.2 V, I
OUT
(STS) = 0 mA
CMOS Inputs, V
CC
= V
CC
Max, V
CCQ
= V
CCQ
Max using standard 8 word page mode
reads. Device is enabled. f = 5 MHz, I
OUT
= 0 mA
CMOS Inputs, V
CC
= V
CC
Max, V
CCQ
= V
CCQ
Max using standard 8 word page mode
reads. Device is enabled. f = 33 MHz, I
OUT
= 0 mA
CMOS Inputs, V
PEN
= V
CC
TTL Inputs, V
PEN
= V
CC
CMOS Inputs, V
PEN
= V
CC
TTL Inputs, V
PEN
= V
CC
Device is enabled
Notes
1
1
50
I
CCS
V
CC
Standby Current
0.71
I
CCD
V
CC
Power‐Down Current
50
15
I
CCR
8‐Word Page
30
I
CCW
I
CCE
I
CCBC
I
CCWS
I
CCES
V
CC
Program or Set Lock‐Bit Current
V
CC
Block Erase or V
CC
Blank Check or
Clear Block Lock‐Bits Current
V
CC
Program Suspend or Block Erase
Suspend Current
35
40
35
40
‐
400
µA
1,2,3
2
400
20
mA
µA
mA
1,3
54
60
70
70
80
10
mA
mA
mA
mA
mA
mA
1,4
1,4
1,5
Notes
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds).
2. Includes STS.
3. CMOS inputs are either VCC ± 0.2 V or VSS ± 0.2 V. TTL inputs are either VIL or VIH.
4. Sampled, not 100% tested.
5. ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend mode, the
device’s current draw is ICCR and ICCWS.
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
4
DC Voltage specifications
V
CCQ
Symbol
V
IL
V
IH
V
CC
Parameter
Input Low Voltage
Input High Voltage
Min
‐0.5
2.0
‐
V
OL
Output Low Voltage
‐
0.2
V
2.7 ‐ 3.6V
2.7 ‐ 3.6V
Max
0.8
V
CCQ
+0.5
0.4
Units
V
V
V
V
CC
= V
CC
Min
V
CCQ
= V
CCQ
Min
I
OL
= 2 mA
V
CC
= V
CC
Min
V
CCQ
= V
CCQ
Min
I
OL
= 100 µA
V
CC
= V
CC
Min
V
CCQ
= V
CCQ
Min
I
OH
= 2.5 mA
V
CC
= V
CC
Min
V
CCQ
= V
CCQ
Min
I
OH
= 100 µA
AS28F128J3A
Q-Flash
PEM
Test Conditions
‐
‐
Notes
2,5,6
2,5,6
1,2
0.85 × V
CCQ
V
OH
Output High Voltage
V
CCQ
– 0.2
V
PENLK
V
PENH
V
LKO
V
PEN
Lockout during Program,
Erase and Lock‐Bit Operations
V
PEN
during Block Erase, Program,
or Lock‐Bit Operations
V
CC
Lockout Voltage
‐
V
‐
1,2
‐
2.7
‐
2.2
3.6
2.0
V
V
V
‐
‐
‐
2,3
3
4
Notes
1. Includes STS.
2. Sampled, not 100% tested.
3. Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min),
and above VPENH (max).
4. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above
VCC (max).
5. Includes all operational modes of the device.
6. Input/Output signals can undershoot to -1.0V referenced to VSS and can overshoot to VCCQ + 1.0V for duration of 2ns or less, the VCCQ valid range is referenced to VSS.
AS28F128J3A
Rev. 5.8 8/13
Micross Components reserves the right to change products or specifications without notice.
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