Intel StrataFlash® Wireless Memory
(L30)
28F640L30, 28F128L30, 28F256L30
Datasheet
Product Features
High performance Read-While-Write/Erase
— 85 ns initial access
— 52 MHz with zero wait state, 17 ns clock-to-
data output synchronous-burst mode
— 25 ns asynchronous-page mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(BEFP) at 5 µs/byte (Typ)
— 1.8 V low-power buffered programming at
7 µs/byte (Typ)
■
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64-Mbit and 128-
Mbit devices
— Multiple 16-Mbit partitions: 256-Mbit devices
— Four 16-Kword parameter blocks: top or
bottom configurations
— 64-Kword main blocks
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Status register for partition and device status
■
Power
— V
CC
(core) = 1.7 V - 2.0 V
— V
CCQ
(I/O) = 2.2 V - 3.3 V
— Standby current: 30 µA (Typ) for 256-Mbit
— 4-Word synchronous read current: 16 mA (Typ)
at 52 MHz
— Automatic Power Savings mode
■
Security
— OTP space:
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
• Additional 2048 user-programmable OTP bits
— Absolute write protection: V
PP
= GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
■
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Intel
®
Flash Data Integrator (FDI) optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
■
Quality and Reliability
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology (0.13 µm)
■
Density and Packaging
— 64-, 128-, and 256-Mbit density in VF BGA
packages
— 128/0 and 256/0 Density in Stacked-CSP
— 16-bit wide data bus
■
The Intel StrataFlash
®
wireless memory (L30) product is the latest generation of Intel
StrataFlash
®
memory devices featuring flexible, multiple-partition, dual operation. It provides
high performance synchronous-burst read mode and asynchronous read mode using 1.8 V low-
voltage, multi-level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one
partition while code execution or data reads take place in another partition. This dual-operation
architecture also allows a system to interleave code operations while program and erase
operations take place in the background.
The L30 device is manufactured using Intel
®
0.13 µm ETOX™ VIII process technology. It is
available in industry-standard chip scale packaging.
Order Number: 251903, Revision: 008
April 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or
in nuclear facility applications.
Legal Lines and Disclaimers
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by
estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at
http://www.intel.com.
Copyright © 2005, Intel Corporation. All Rights Reserved.
April 2005
2
Intel StrataFlash® Wireless Memory (L30)
Order Number: 251903, Revision: 008
Datasheet
Intel StrataFlash® Wireless Memory (L30)
Contents
1.0
Introduction
............................................................................................................................ 7
1.1
1.2
1.3
Nomenclature .................................................................................................................. 7
Acronyms ........................................................................................................................ 7
Conventions .................................................................................................................... 8
2.0
3.0
Functional Overview
........................................................................................................... 9
Package Information
.........................................................................................................10
3.1
3.2
VF BGA Packages ........................................................................................................10
SCSP Packages ............................................................................................................12
Signal Ballout ................................................................................................................14
4.1.1 VF BGA Package Ballout .................................................................................14
4.1.2 SCSP Package Ballout.....................................................................................16
Signal Descriptions........................................................................................................17
4.2.1 VF BGA Package Signal Descriptions..............................................................17
4.2.2 128/0 and 256/0 SCSP Package Signal Descriptions ......................................19
Memory Map .................................................................................................................21
Absolute Maximum Ratings...........................................................................................23
Operating Conditions.....................................................................................................23
DC Current Characteristics ...........................................................................................24
DC Voltage Characteristics ...........................................................................................25
AC Test Conditions .......................................................................................................26
Capacitance ..................................................................................................................27
AC Read Specifications for 64-Mbit and 128-Mbit Densities.........................................28
AC Read Specifications for 256-Mbit Density ...............................................................29
AC Write Specifications .................................................................................................34
Program and Erase Characteristics ..............................................................................38
Power Up and Down .....................................................................................................39
Reset Specifications ......................................................................................................39
Power Supply Decoupling .............................................................................................40
Automatic Power Saving ...............................................................................................41
Bus Operations.............................................................................................................. 42
9.1.1 Reads ...............................................................................................................43
9.1.2 Writes ...............................................................................................................43
9.1.3 Output Disable..................................................................................................43
9.1.4 Standby ............................................................................................................43
4.0
Ballout and Signal Descriptions
..................................................................................14
4.1
4.2
4.3
5.0
Maximum Ratings and Operating Conditions
........................................................23
5.1
5.2
6.0
Electrical Specifications
..................................................................................................24
6.1
6.2
7.0
AC Characteristics
.............................................................................................................26
7.1
7.2
7.3
7.4
7.5
7.6
8.0
Power and Reset Specifications
..................................................................................39
8.1
8.2
8.3
8.4
9.0
Device Operations
.............................................................................................................42
9.1
Datasheet
Intel StrataFlash® Wireless Memory (L30)
Order Number: 251903, Revision: 008
April 2005
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Intel StrataFlash® Wireless Memory (L30)
9.2
9.3
9.1.5 Reset ................................................................................................................ 43
Device Commands ........................................................................................................ 44
Command Definitions .................................................................................................... 45
Asynchronous Page-Mode Read .................................................................................. 47
Synchronous Burst-Mode Read .................................................................................... 47
10.2.1 Burst Suspend.................................................................................................. 48
Read Configuration Register (RCR).............................................................................. 48
10.3.1 Read Mode....................................................................................................... 49
10.3.2 Latency Count .................................................................................................. 50
10.3.3 WAIT Polarity ................................................................................................... 51
10.3.3.1WAIT Signal Function.......................................................................... 51
10.3.4 Data Hold ......................................................................................................... 52
10.3.5 WAIT Delay ...................................................................................................... 53
10.3.6 Burst Sequence................................................................................................ 53
10.3.7 Clock Edge ....................................................................................................... 54
10.3.8 Burst Wrap ....................................................................................................... 54
10.3.9 Burst Length ..................................................................................................... 54
Word Programming ....................................................................................................... 55
11.1.1 Factory Word Programming ............................................................................. 56
Buffered Programming .................................................................................................. 56
Buffered Enhanced Factory Programming .................................................................... 57
11.3.1 Buffered EFP Requirements and Considerations ............................................ 57
11.3.2 Buffered EFP Setup Phase .............................................................................. 58
11.3.3 Buffered EFP Program/Verify Phase................................................................ 58
11.3.4 Buffered EFP Exit Phase.................................................................................. 59
Program Suspend ......................................................................................................... 59
Program Resume .......................................................................................................... 60
Program Protection ....................................................................................................... 60
Block Erase ................................................................................................................... 61
Erase Suspend.............................................................................................................. 61
Erase Resume............................................................................................................... 62
Erase Protection............................................................................................................ 62
Block Locking ................................................................................................................ 63
13.1.1 Lock Block ........................................................................................................ 63
13.1.2 Unlock Block..................................................................................................... 63
13.1.3 Lock-Down Block.............................................................................................. 63
13.1.4 Block Lock Status............................................................................................. 64
13.1.5 Block Locking During Suspend ........................................................................ 64
Protection Registers ...................................................................................................... 65
13.2.1 Reading the Protection Registers..................................................................... 66
13.2.2 Programming the Protection Registers ............................................................ 67
13.2.3 Locking the Protection Registers...................................................................... 67
10.0
Read Operations
................................................................................................................. 47
10.1
10.2
10.3
11.0
Programming Operations
............................................................................................... 55
11.1
11.2
11.3
11.4
11.5
11.6
12.0
Erase Operations
................................................................................................................ 61
12.1
12.2
12.3
12.4
13.0
Security Modes
................................................................................................................... 63
13.1
13.2
April 2005
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Intel StrataFlash® Wireless Memory (L30)
Order Number: 251903, Revision: 008
Datasheet
Intel StrataFlash® Wireless Memory (L30)
14.0
Dual-Operation Considerations
....................................................................................68
14.1
14.2
Memory Partitioning ......................................................................................................68
Read-While-Write Command Sequences .....................................................................68
14.2.1 Simultaneous Operation Details .......................................................................69
14.2.2 Synchronous and Asynchronous RWW Characteristics and Waveforms ........69
14.2.2.1Write operation to asynchronous read transition .................................69
14.2.2.2Write to synchronous read operation transition ...................................69
14.2.2.3Write Operation with Clock Active .......................................................70
14.2.3 Read Operation During Buffered Programming Flowchart...............................70
Simultaneous Operation Restrictions ............................................................................71
Read Status Register ....................................................................................................72
15.1.1 Clear Status Register .......................................................................................73
Read Device Identifier ...................................................................................................73
CFI Query ......................................................................................................................74
14.3
15.0
Special Read States
..........................................................................................................72
15.1
15.2
15.3
Appendix A
Appendix B
Appendix C
Appendix D
Appendix E
Write State Machine (WSM)
...........................................................................75
Flowcharts
............................................................................................................82
Common Flash Interface
................................................................................90
Additional Information
...................................................................................100
Ordering Information
......................................................................................101
Datasheet
Intel StrataFlash® Wireless Memory (L30)
Order Number: 251903, Revision: 008
April 2005
5
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