Features
•
Single 2.7V - 3.6V Supply
•
Serial Peripheral Interface (SPI) Compatible
– Supports SPI Modes 0 and 3
– Supports RapidS Operation
– Supports Dual- and Quad-Input Program
– Supports Dual- and Quad-Output Read
Very High Operating Frequencies
– 100 MHz for RapidS
– 85 MHz for SPI
– Clock-to-Output (t
V
) of 5 ns Maximum
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
– Uniform 4-Kbyte Block Erase
– Uniform 32-Kbyte Block Erase
– Uniform 64-Kbyte Block Erase
– Full Chip Erase
Individual Sector Protection with Global Protect/Unprotect Feature
– 64 Sectors of 64-Kbytes Each
Hardware Controlled Locking of Protected Sectors via WP Pin
Sector Lockdown
– Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
128-Byte Programmable OTP Security Register
Flexible Programming
– Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
– 1.5 ms Typical Page Program (256 Bytes) Time
– 50 ms Typical 4-Kbyte Block Erase Time
– 250 ms Typical 32-Kbyte Block Erase Time
– 400 ms Typical 64-Kbyte Block Erase Time
Program and Erase Suspend/Resume
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
– 7 mA Active Read Current (Typical at 20 MHz)
– 5 µA Deep Power-Down Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
– 8-lead SOIC (150-mil and 208-mil wide)
– 16-lead SOIC (300-mil wide)
– 8-pad Very Thin DFN (5 x 6 x 0.6 mm)
•
•
•
•
•
•
•
•
32-Megabit
2.7-volt
Minimum
SPI Serial Flash
Memory with
Dual-I/O and
Quad-I/O
Support
AT25DQ321A
•
•
•
•
•
Preliminary
•
•
•
•
8718A–DFLASH–04/10
1.
Description
The AT25DQ321A is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external
RAM for execution. The flexible erase architecture of the AT25DQ321A, with its erase granularity as small as 4-
Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices.
The physical sectoring and the erase block sizes of the AT25DQ321A have been optimized to meet the needs of
today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the
memory space can be used much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with
large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added while still maintaining the same
overall device density.
The AT25DQ321A also offers a sophisticated method for protecting individual sectors against erroneous or
malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a
system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory
array securely protected. This is useful in applications where program code is patched or updated on a subroutine
or module basis, or in applications where data storage segments need to be modified without running the risk of
errant modifications to the program code segments. In addition to individual sector protection capabilities, the
AT25DQ321A incorporates Global Protect and Global Unprotect features that allow the entire memory array to be
either protected or unprotected all at once. This reduces overhead during the manufacturing process since sectors
do not have to be unprotected one-by-one prior to initial programming.
To take code and data protection to the next level, the AT25DQ321A incorporates a sector lockdown mechanism
that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only.
This addresses the need of certain secure applications that require portions of the Flash memory array to be
permanently protected against malicious attempts at altering program code, data modules, security information, or
encryption/decryption algorithms, keys, and routines. The device also contains a specialized OTP (One-Time
Programmable) Security Register that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-volt systems, the AT25DQ321A supports read, program, and erase operations
with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
2
AT25DQ321A [Preliminary]
8718A–DFLASH–04/10
AT25DQ321A [Preliminary]
2.
Pin Descriptions and Pinouts
Table 2-1.
Symbol
Pin Descriptions
Name and Function
CHIP SELECT:
Asserting the CS pin selects the device. When the CS pin is
deasserted, the device will be deselected and normally be placed in standby
mode (not Deep Power-Down mode), and the SO pin will be in a high-
impedance state. When the device is deselected, data will not be accepted on
the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a
low-to-high transition is required to end an operation. When ending an internally
self-timed operation such as a program or erase cycle, the device will not enter
the standby mode until the completion of the operation.
SERIAL CLOCK:
This pin is used to provide a clock to the device and is used
to control the flow of data to and from the device. Command, address, and input
data present on the SI pin or I/O pins is always latched in on the rising edge of
SCK, while output data on the SO pin or I/O pins is always clocked out on the
falling edge of SCK.
SERIAL INPUT (I/O
0
):
The SI pin is used to shift data into the device. The SI
pin is used for all data input including command and address sequences. Data
on the SI pin is always latched in on the rising edge of SCK.
With the Dual-Input and Quad-Input Byte/Page Program commands, the SI pin
is used as an input pin (I/O
0
) in conjunction with other pins to allow two bits (on
I/O
1-0
) or four bits (on I/O
3-0
) of data to be clocked in on every rising edge of
SCK. With the Dual-Output and Quad-Output Read Array commands, the SI pin
becomes an output pin (I/O
0
) and, along with other pins, allows two bits (on I/O
1-
0
) or four bits (on I/O
3-0
) of data to be clocked out on every falling edge of SCK.
To maintain consistency with SPI nomenclature, the SI (I/O
0
) pin will be
referenced as SI throughout the document with exception to sections dealing
with the Dual-Input and Quad-Input Byte/Page Program commands as well as
the Dual-Output and Quad-Output Read Array commands in which it will be
referenced as I/O
0
.
Data present on the SI pin will be ignored whenever the device is deselected
(CS is deasserted).
SERIAL OUTPUT (I/O
1
):
The SO pin is used to shift data out from the device.
Data on the SO pin is always clocked out on the falling edge of SCK.
With the Dual-Input and Quad-Input Byte/Page Program commands, the SO pin
becomes an input pin (I/O
1
) and, along with other pins, allows two bits (on I/O
1-0
)
or four bits (on I/O
3-0
) of data to be clocked in on every rising edge of SCK. With
the Dual-Output and Quad-Output Read Array commands, the SO pin is used
as an output pin (I/O
1
) in conjunction with other pins to allow two bits (on I/O
1-0
)
or four bits (on I/O
3-0
) of data to be clocked out on every falling edge of SCK. To
maintain consistency with SPI nomenclature, the SO (I/O
1
) pin will be
referenced as SO throughout the document with exception to sections dealing
with the Dual-Input and Quad-Input Byte/Page Program commands as well as
the Dual-Output and Quad-Output Read Array commands in which it will be
referenced as I/O
1
.
The SO pin will be in a high-impedance state whenever the device is deselected
(CS is deasserted).
Asserted
State
Type
CS
Low
Input
SCK
-
Input
SI (I/O
0
)
-
Input/Output
SO (I/O
1
)
-
Input/Output
3
8718A–DFLASH–04/10
Table 2-1.
Symbol
Pin Descriptions (Continued)
Name and Function
WRITE PROTECT (I/O
2
):
The WP# pin controls the hardware locking feature of
the device.
See “Protection Commands and Features” on page 23.
for more
details on protection features and the WP pin.
With the Quad-Input Byte/Page Program command, the WP pin becomes an
input pin (I/O
2
) and, along with other pins, allows four bits (on I/O
3-0
) of data to
be clocked in on every rising edge of SCK. With the Quad-Output Read Array
command, the WP pin becomes an output pin (I/O
2
) and, when used with other
pins, allows four bits (on I/O
3-0
) of data to be clocked out on every falling edge of
SCK. The QE bit in the Configuration Register must be set in order for the WP
pin to be used as an I/O data pin.
The WP pin must be driven at all times or pulled-high using an external pull-up
resistor.
HOLD (I/O
3
):
The HOLD pin is used to temporarily pause serial communication
without deselecting or resetting the device. While the HOLD pin is asserted,
transitions on the SCK pin and data on the SI pin will be ignored, and the SO pin
will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order
for a Hold condition to start. A Hold condition pauses serial communication only
and does not have an affect on internally self-timed operations such as a
program or erase cycle.
See “Hold” on page 49.
for additional details on the
Hold operation.
With the Quad-Input Byte/Page Program command, the HOLD pin becomes an
input pin (I/O
3
) and, along with other pins, allows four bits (on I/O
3-0
) of data to
be clocked in on every rising edge of SCK. With the Quad-Output Read Array
command, the HOLD pin becomes an output pin (I/O
3
) and, when used with
other pins, allows four bits (on I/O
3-0
) of data to be clocked out on every falling
edge of SCK. The QE bit in the Configuration Register must be set in order for
the HOLD pin to be used as an I/O data pin.
The HOLD pin must be driven at all times or pulled-high using an external pull-
up resistor.
DEVICE POWER SUPPLY:
The V
CC
pin is used to supply the source voltage to
the device.
Operations at invalid V
CC
voltages may produce spurious results and should not
be attempted.
GROUND:
The ground reference for the power supply. GND should be
connected to the system ground.
Asserted
State
Type
WP (I/O
2
)
Low
Input/Output
HOLD (I/O
3
)
Low
Input/Output
V
CC
-
Power
GND
-
Power
Figure 2-1.
Pin Configurations
8-SOIC
8-UDFN
V
CC
HOLD (I/O
3
)
SCK
SI (I/O
0
)
CS
8
SO (I/O
1
)
7
WP (I/O
2
)
6
GND
5
1
V
CC
2
HOLD (I/O
3
)
3
SCK
4
SI (I/O
0
)
16-SOIC
NC
V
CC
NC
NC
NC
NC
CS
SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SCK
SI
NC
NC
NC
NC
GND
WP
CS
SO (I/O
1
)
WP (I/O
2
)
GND
1
2
3
4
8
7
6
5
4
AT25DQ321A [Preliminary]
8718A–DFLASH–04/10
AT25DQ321A [Preliminary]
3.
Block Diagram
Figure 3-1.
Block Diagram
CS
CONTROL AND
PROTECTION LOGIC
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
SCK
SI (I/O0)
SO (I/O1)
INTERFACE
CONTROL
AND
LOGIC
ADDRESS LATCH
Y-DECODER
Y-GATING
WP (I/O2)
HOLD (I/O3)
X-DECODER
FLASH
MEMORY
ARRAY
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands
4.
Memory Array
To provide the greatest flexibility, the memory array of the AT25DQ321A can be erased in four levels of granularity
including a full chip erase. In addition, the array has been divided into physical sectors of uniform size, of which
each sector can be individually protected from program and erase operations. The size of the physical sectors is
optimized for both code and data storage applications, allowing both code and data segments to reside in their own
isolated regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as well as the
breakdown of each physical sector.
5
8718A–DFLASH–04/10
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