SDC-14560
SYNCHRO-TO-DIGITAL CONVERTER
DESCRIPTION
The SDC-14560 is a series of high-reli-
ability synchro or resolver-to-digital con-
verters with user-programmable resolu-
tion of 10, 12, 14, or 16 bits. Other fea-
tures of the SDC-14560 are high-quali-
ty velocity output and hermetic seal.
User-programmable resolution has
been designed into the SDC-14560 to
increase the capabilities of modern
motion control systems. The precise
positioning attained at 16-bit resolu-
tion and fast tracking of a 10-bit
device are now available from one 36-
pin double DIP hybrid. Velocity output
(VEL) from the SDC-14560 is a
ground-based voltage of 0 to
±10 VDC with a linearity to 0.7%.
Output voltage is positive for an
increasing angle.
The SDC-14560 series accepts
broadband inputs: 360 Hz to 1 kHz, or
47 Hz to 1 kHz. The digital angle out-
put from the SDC-14560 is a natural
binary code, parallel positive logic
and is TTL/CMOS compatible.
Synchronization to a computer is
accomplished via a converter busy
(CB) and an inhibit (INH) input.
FEATURES
•
Programmable Resolution:
10, 12, 14 or 16 Bits
•
High-Quality Velocity Output
•
Eliminates Tachometer
•
Accuracy to ±1.3 Arc
Minutes
APPLICATIONS
Because of its high reliability, accura-
cy, small size, and low power con-
sumption, the SDC-14560 is ideal for
the most stringent and severe indus-
trial and military ground or avionics
applications. All models are available
with MIL-PRF-38534 processing as a
standard option.
Designed with three-state output, the
SDC-14560 is especially well suited
for use with computer-based systems.
Among the many possible applica-
tions are radar and navigation sys-
tems, fire control systems, flight
instrumentation, and flight trainers or
simulators.
•
Small Size
•
Synchro or Resolver Input
•
Synthesized Reference
Eliminates 180° Lock-Up
SOLID STATE SYNCHRO INPUT OPTION
SOLID STATE RESOLVER INPUT OPTION
SOLID STATE RESOLVER INPUT OPTION
SIN
θ
COS
θ
VOLTAGE
FOLLOWER
BUFFER
SIN
θ
COS
θ
INTERNAL
DC
REFERENCE
BIT
RL
+15 V
-15 V
S1
S2
S3
ELECTRONIC
SCOTT T
SIN
θ
COS
θ
S1
S2
S3
S4
RESOLVER
CONDITIONER
SIN
θ
COS
θ
INPUT OPTIONS
V
REF IN
RH
REFERENCE
CONDITIONER
R
SYNTHESIZED
REF
BIT DETECT
DIFF
GAIN
OF 2
e
DIFF
GAIN OF
2, 7
SIN
θ
INPUT OPTION
COS
θ
HIGH ACCURACY
CONTROL
TRANSFORMER
VEL
GAIN
e
SIN
(θ-φ)
DEMOD
D
ERROR
PROCESSOR
VEL
T
VCO
U
E
1 LSB ANTIJITTER FEEDBACK
16-BIT CT
TRANSPARENT
LATCH
U
50 ns DELAY
T
0.4-1 µs
CB
+5 V
DIGITAL
ANGLE
φ
16-BIT U-D
COUNTER
Q
INH
3 STATE
TTL BUFFER
16-BIT OUTPUT
TRANSPARENT
LATCH
3 STATE
TTL BUFFER
EDGE
T
TRIGGERED
LATCH
A
B
RESOLUTION CONTROL
INHIBIT
TRANSPARENT
LATCH
POWER
SUPPLY
CONDITIONER
INH
+10 V
INTERNAL DC
REF V (+5 V)
+15
EM
BITS 1-8
BITS 9-16
EL
S
FIGURE 1. SDC-14560 BLOCK DIAGRAM
©
1987, 1999 Data Device Corporation
TABLE 1. SDC-14560 SPECIFICATIONS
Apply over temperature range power supply range reference frequency
and amplitude ranges; 10% signal amplitude variation; and up to 10%
harmonic distortion in the reference.
PARAMETER
RESOLUTION
(1)
ACCURACY
(2)
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
CHARACTERISTICS
Carrier Frequency Ranges
Nominal 400 Hz Units
Nominal 60 Hz Units
Voltage Range
Input Impedance
Single Ended
Differential
Common Mode Range
SIGNAL INPUT
CHARACTERISTICS
(voltage options and minimum
input impedance balanced)
Synchro
Zin Line to Line
Zin Each Line to Gnd
Resolver
Zin Single Ended
Zin Differential
Zin Each Line to Gnd
Common Mode Range
Direct (1.0 VL-L)
Input Signal Type
UNIT
Bits
Min
LSB
LSB
VALUE
10, 12, 14, or 16
±6, ±4, ±2, or ±1 +1LSB
1 max
1 max in the 16th bit
TABLE 1. SDC-14560 SPECIFICATIONS (CONTD)
PARAMETER
Output Parallel Data
UNIT
bits
VALUE
10, 12, 14, or 16 parallel
lines; natural binary angle,
positive logic
0.4 to 1 µs positive pulse;
leading edge initiates
counter update.
Logic 0 for fault.
50 pF plus rated logic drive.
Logic 0; 1 TTL load,
1.6 mA at 0.4 Vmax
Logic 1; 10 TTL loads
0.4 mA at 2.8 V min
High Z; 10 µA//5 pF max
Logic 0; 100 mV max
driving CMOS
Logic 1; +5 V supply minus
100 mV min driving CMOS
Converter Busy (CB)
BIT
Drive Capability
Hz
Hz
Vrms
Ohm
Ohm
V
360-1000
47-1000
4-130
250k min
500k min
210 peak max
500 transient peak
ANALOG OUTPUTS
Velocity (VEL)
AC error (e)
Ohm
Ohm
Ohm
Ohm
Ohm
V
11.8 VL-L
17.5k
11.5k
11.8 VL-L
23k
46k
23k
60 max
90 VL-L
130k
85k
26 VL-L
50k
100k
50k
60 max
Load
DYNAMIC
CHARACTERISTICS
POWER SUPPLY
CHARACTERISTICS
Nominal Voltage
Voltage Range
Max Voltage w/o Damage
Current
TEMPERATURE RANGES
Operating
-30X
-10X
Storage
THERMAL RESISTANCE
Junction to Case,
θ
jc
Junction to Ambient,
θ
ja
PHYSICAL
CHARACTERISTICS
Size
See TABLES 3 and 4
mV rms 50 per LSB of error
(10-bit mode)
25 per LSB of error
(12-bit mode)
12.5 per LSB of error
(14-bit mode)
6.3 per LSB of error
(16-bit mode)
kOhm 3 min
See TABLE 3.
sin/cos Voltage Range
Max Voltage w/o Damage
Input Impedance
REFERENCE SYNTHESIZER
±Sig/Ref Phase Shift
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
Vrms
Ohm
sin and cos resolver signals
referenced to converter inter-
nal DC reference V.
1 V nominal, 1.15 V max
15 V continuous
100 V Peak Transient
Zin > 20M//10 pF
voltage follower
60 max, 45 typ
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
Loading = 30 µA max P.U.
current source
to +5 V//5 pF max
CMOS transient protected
Logic 0 inhibits
Data stable after 0.5 µs
Logic 0 enables
Logic 1 High Z
Logic 0 enables
Logic 1 High Z
Logic 0 for use as CT
B
0
0
1
1
A
0
1
0
1
Resolution
10 bits
12 bits
14 bits
16 bits
+15 V
±%
5
V
+18
mA max 25
+5 V
10
+8
10
-15 V
5
-18
15
Deg
°C
°C
°C
°C/W
°C/W
0 to +70
-55 to +125
-65 to +150
8
20
Inhibit (INH)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 16 (EL)
S (Control Transformer)
Resolution Control (A & B)
(Unused Output Data
Bits Are Set to 0)
Weight
TRANSFORMERS
CHARACTERISTICS
(See ordering information for
list of Transformers. Reference
Transformers are Optional for
Both Solid-State and Voltage
Follower Input Options.)
400 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Voltage Range
Input Impedance
Breakdown Voltage to GND
in. (mm) 1.9 x 0.78 x 0.21
(48.3 x 19.8 x 5.3)
36-Pin Double Dip
oz. (g) 0.7 max (20)
360 - 1000 Hz
18 - 130 V
40 kΩ min
1200 V peak
2
TABLE 1. SDC-14560 SPECIFICATIONS (CONTD)
PARAMETER
TRANSFORMERS
CHARACTERISTICS (contd)
Signal Transformer
Carrier Frequency Range
Breakdown Voltage to GND
Minimum Input Impedances
(Balanced)
90 V L-L
26 V L-L
11.8 V L-L
60 Hz TRANSFORMERS
Reference Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common-Mode Voltage
Output Description
UNIT
VALUE
360- 1000 Hz
700 V peak
Synchro Z
IN
(Z
SO
) Resolver Z
lN
180
Ω
-
20k
Ω
100k
Ω
30k
Ω
30k
Ω
sin(θ + 120°)cosωt, and sin(θ + 240°)cosωt are internally con-
verted to resolver format; sinθcosωt and cosθcosωt. Direct inputs
accept 1 Vrms inputs in resolver form, (sinθcosωt and cosθ−
cosωt) and are buffered prior to conversion. FIGURE 2 illustrates
synchro and resolver signals as a function of the angle
θ.
The solid state signal and reference inputs are true differential
inputs with high AC and DC common mode rejection.
Input
impedance is maintained with power off.
S1-S3 = V
MAX
MAX
SINθ
+V
In Phase with
RL-RH of Converter
and R2-R1 of CX.
Output Voltage
In Phase with
RH-RL of Converter
and R2-R4 of RX.
Power Required
Signal Transformer
Carrier Frequency Range
Input Voltage Range
Input Impedance
Input Common Mode Voltage
Output Description
47 - 440 Hz
80 - 138 V rms; 115 V rms
nominal resistive
600 kΩ min resistive
500 V rms transformer isolated
+R (in phase with RH-RL)
and - R (in phase with RL- RH)
derived from op-amps. Short
Circuit proof.
3.0 V nominal riding on ground
reference V. Output Voltage level
tracks input level.
4 mA typ, 7 mA max from
+15 V supply.
47 - 440 Hz
10 - 100 V rms L-L; 90 V rms
L- L nominal
148 kΩ min L-L balanced
resistive
±500 V rms transformer isolated
Resolver output,
- sine (- S) + cosine (+C)
derived from op-amps.
Short circuit proof.
1.0 V rms nominal riding on
ground reference V.
Output voltage level tracks
input level.
4 mA typ, 7 mA max from
+15 V supply.
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
-V
MAX
S3-S2 = V
S2-S1 = V
MAX
SIN(θ
+ 120°)
MAX
SIN(θ
+ 240°)
Standard Synchro Control Transmitter (CX) Outputs as a Function of CCW Rotation
From Electrical Zero (EZ).
+V
S2-S4 = V
MAX
MAX
COS
θ
0
360
30
90
150
210
270
330
θ
CCW
(DEGREES)
-V
MAX
S1-S3 = –V
MAX
SIN(θ)
Standard Resolver Control Transmitter (RX) Outputs as a Function of CCW
Rotation From Electrical Zero (EZ) With R2-R4 Excited.
FIGURE 2. SYNCHRO AND RESOLVER SIGNALS
SOLID-STATE BUFFER INPUT PRODUCTION -
TRANSIENT VOLTAGE SUPPRESSION
The solid-state signal and reference inputs are true differential
inputs with high AC and DC common rejection, so most applica-
tions will not require units with isolation transformers. Input
impedance is maintained with power off. The current AC peak
+DC common mode voltage should not exceed the values in
TABLE 1.
The 90 V line-to-line systems may have voltage transients which
exceed the 500 V specification. These transients can destroy the
thin-film input resistor network in the hybrid. Therefore, 90 V
L
-
L
solid-state input modules may be protected by installing voltage
suppressors as shown. Voltage transients are likely to occur
whenever synchro or resolver are switched on and off. For
instance, a 1000 V transient can be generated when the prima-
ry of a CX or TX driving a synchro or resolver input is opened.
See FIGURE 3.
Output Voltage
Power Required
Note:
(1) Pin programmable.
(2) See TABLE 6.
INTRODUCTION
The circuit shown in FIGURE 1, the SDC-14560 Block Diagram,
consists of three main parts: the signal input; a feedback loop,
whose elements are the control transformer, demodulator, error
processor, VCO and up-down counter; and digital interface cir-
cuitry including various latches and buffers.
SIGNAL INPUTS
The SDC-14560 series offers three input options: synchro,
resolver, and direct. In a synchro or resolver, shaft angle data is
transmitted as the ratio of carrier amplitudes across the input ter-
minals. Synchro signals, which are of the form sinθcosωt,
FEEDBACK LOOP
The feedback loop produces a digital angle
φ
which tracks the
analog input angle
θ
to within the specified accuracy of the con-
3
CR1
S1
CR2
FOR 90 V SYNCHRO INPUTS
S3
S3
RH
CR3
S2
S2
RL
S1
HYBRID
1N6071A
phase with the signal input, and quadrature errors will therefore
be eliminated. The synthesized reference circuit also eliminates
the 180° false error null hangup.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. A digital position error will result due to the
interaction of this quadrature voltage and a reference phase shift
between the converter signal and reference inputs. The magni-
tude of this error is given by the following formula:
Error = Quad/F.S. signal * tan(α)
S1
S2
CR1, CR2, and CR3 are 1N6136A, bipolar transient voltage suppressors
or equivalent.
FOR 90 V RESOLVER INPUTS
S1
S2
90 V L-L
RESOLVER
INPUT
S3
S4
CR4
CR5
S3
S4
HYBRID
Where: Error is in radians
Quad/F.S. signal is per unit quadrature input level.
α
= signal to reference phase shift in degrees.
A typical example of the magnitude of this source of error is as
follows:
Quad/F.S. signal = .001
α
=6
Error = 0.35 min
≈1
LSB in the 16th bit.
Note: Quad/F.S. is composed of static quadrature which is spec-
ified by the resolver or synchro supplier plus the speed voltage
which is given by:
Speed Voltage = rotational speed/carrier frequency
Where: Speed Voltage is the per unit ratio of electrical rotational
speed in RPS divided by carrier frequency in Hz.
This error is totally negligible for up to 14-bit converters. For 16-
bit converters, where the highest accuracy possible is needed
and where the quadrature and phase shift specifications can be
higher, this source of error could be significant. The reference
synthesizer circuit in the converter which derives the reference
from the input signal essentially sets
α
to zero resulting in com-
plete rejection of the quadrature.
CR4 and CR5 are 1N6136A, bipolar transient voltage suppressors or equivalent.
FIGURE 3. CONNECTIONS FOR VOLTAGE
TRANSIENT SUPPRESSORS
verter. The control transformer performs the following trigono-
metric computation:
sin(θ -
φ)
= sinθ cosφ - cosθ sinφ
where
θ
is the angle representing the resolver shaft position, and
φ
is the digital angle contained in the up/down counter. The track-
ing process consists of continually adjusting
φ
to make (θ -
φ)
à
0, so that
φ
will represent the shaft position
θ.
The output of the
demodulator is an analog DC level proportional to sin(θ -
φ).
The
error processor receives its input from the demodulator and inte-
grates this sin(θ -
φ)
error signal which then drives a Voltage-
Controlled Oscillator (VCO). The VCO’s clock pulses are accu-
mulated by the up/down counter. The velocity voltage accuracy,
linearity and offset are determined by the quality of the VCO.
Functionally, the up/down counter is an incremental integrator.
Therefore, there are two stages of integration which make the
converter a Type II tracking servo. In a Type II servo, the VCO
always settles to a counting rate which makes dφ/dt equal to
dθ/dt without a lag. The output data will always be fresh and
available as long as the maximum tracking rate of the converter
is not exceeded.
DIGITAL INTERFACE
The digital interface circuitry has three main functions: to latch
the output bits during an inhibit command so that the stable data
can be read; to furnish both parallel and three-state data formats;
and to act as a buffer between the internal CMOS logic and the
external TTL logic.
In the SDC-14560, applying an inhibit command will lock the
data in the transparent latch without interfering with the continu-
ous tracking of the feedback loop. Therefore, the digital angle is
always updated, and the inhibit can be applied for an arbitrary
amount of time. The inhibit transparent latch and the 50 ns delay
are part of the inhibit circuitry. The inhibit circuitry is described in
detail in the logic input/output section.
SYNTHESIZED REFERENCE
The synthesized reference section of the SDC-14560 eliminates
errors caused by quadrature voltage. Due to the inductive nature
of synchros and resolvers, their signals lead the reference signal
(RH and RL) by about 6°. When an uncompensated reference
signal is used to demodulate the control transformer’s output,
quadrature voltages are not completely eliminated. In a 12- or
14-bit converter it is not necessary to compensate for the refer-
ence signal’s phase shift. A 6° phase shift will, however, cause
problems for the one minute accuracy converters. As shown in
FIGURE 1, the converter synthesizes its own cos(ωt +
α)
refer-
ence signal from the sinθcos(ωt +
α),
cosθcos(ωt +
α)
signal
inputs and from the cos
ωt
reference input. The phase angle of
the synthesized reference is determined by the signal input The
reference input is used to choose between the +180° and -180°
phases. The synthesized reference will always be exactly in
LOGIC INPUT/OUTPUT
Logic angle outputs consist of 10, 12, 14 or 16 parallel data bits
and CONVERTER BUSY (CB). All logic outputs are short-circuit
proof to ground and +5 Volts. The CB output is a positive, 0.4 to
1.0 µs pulse. Data changes about 50 ns after the leading edge of
the pulse because of an internal delay. Data is valid 0.2 µs after
the leading edge of CB, the angle is determined by the sum of
the bits at logic “1”. Digital outputs are three-state and two bytes
wide; bits 1-8 (MSBs) are enabled by the signal EM, bits 9-16
4
(LSBs) are enabled by the signal EL. Outputs are valid (logic “1”
or “0”) 150 ns max after setting EM or EL low, and are high
impedance within 100 ns max of setting EM or EL high. Both EM
and EL are internally pulled-up to +5 V at 30 µA max.
The inhibit (INH) input locks the transparent latch so the bits will
remain stable while data is being transferred (see FIGURE 1).
The output is stable 0.5 µs after INH is driven to logic “0”, see
FIGURE 4. A logic “0” at the T input latches the data, and a logic
“1” applied to T will allow the bits to change. The inhibit transpar-
ent latch prevents the transmission of invalid data when there is
an overlap between CB and INH. While the counter is not being
updated, CB is at logic “0” and the INH latch is transparent.
When CB goes to logic “1” the INH latch is locked. If CB occurs
after INH has been applied, the latch will remain locked and its
data will not change until CB returns to logic “0”; if INH is applied
during CB, the latch will not lock until the CB pulse is over. The
purpose of the 50 ns delay is to prevent a race condition between
CB and INH where the up-down counter begins to change as an
INH is applied. Whenever an input angle change occurs, the
converter changes the digital angle in 1 LSB steps and gener-
ates a converter busy pulse. Output data change is initiated by
the leading edge of the CB pulse, delayed by 50 ns, nominal.
Valid data is available at the outputs 0.2 µs after the leading edge
of CB, see FIGURE 5.
TABLE 2. DIGITAL ANGLE OUTPUTS
BIT
1 MSB
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DEG/BIT
180.0
90.0
45.0
22.5
11.25
5.625
2.813
1.406
0.7031
0.3516
0.1758
0.0879
0.0439
0.0220
0.0110
0.0055
MIN/BIT
10800.0
5400.0
2700.0
1350.0
675.0
337.5
168.75
84.38
42.19
21.09
10.55
5.27
2.64
1.32
0.66
0.33
Note: EM enables the MSBs and EL enables the LSBs.
changing the resolution, inputs A and B are latched internally on
the trailing edge of CB, as illustrated in FIGURE 6.
Digital angle outputs are buffered and are provided in a two byte
format. The first byte always contains the MSBs (bits 1-8) and is
enabled by placing EM (pin 26) to logic “0”. Depending on the
user-programmed resolution, the second byte will have bits 9
through 10, 9 through 12, or 9 through 14, while operating at 10-,
12-, or 14-bit resolution, respectively. Placing EL (pin 25) to logic “0”
enables the second byte, the LSBs. A logic “0” will be present on
all the unused least significant bits. TABLE 2 lists the deg/bit for
the digital angle outputs.
RESOLUTION CONTROL
Resolution control is via two logic inputs, A and B. The resolution
can be changed during converter operation so the appropriate
resolution and velocity dynamics can be changed as needed. To
ensure that no race conditions exist between counting and
BUILT-IN-TEST
The Built-ln-Test output (BIT) monitors the level of error (D) from
the demodulator. D represents the difference in the input and
output angles and ideally should be zero; if it exceeds approxi-
mately 65 LSBs (of the selected resolution) the logic level at BIT
will change from a logic 1 to logic 0. This condition will occur dur-
ing a large step and reset after the converter settles out. BIT will
also change to logic 0 for an over-velocity condition, because the
converter loop cannot maintain input-output or if the converter
malfunctions where it cannot maintain the loop at a null. BIT will
also be set if a total Loss-of-Signal (LOS) and/or a Loss-of-
Reference (LOR) occurs.
ASYNCHROUS TO CB
INH
DATA
FIGURE 4. INHIBIT TIMING DIAGRAM
6.1
µs
MIN
DEPENDS ON dφ/dt
,, ,,
,, ,,
0.5
µs
VALID
CB
0.2
µs
DATA
FIGURE 5. CONVERTER BUSY TIMING DIAGRAM
CB
, ,
0.4-1.0
µs
VALID
DYNAMIC PERFORMANCE
A Type II servo loop (Kv =
∞)
and very high acceleration constants
give the SDC-14560 superior dynamic performance, as listed in
TABLE 2. If the power supply voltages are not the ±15 V DC nom-
inal values, the specified input rates will increase or decrease in
proportion to the fractional change in voltage. A Control Loop
Block Diagram is shown in FIGURE 7, and an Open Loop Bode
Plot is shown in FIGURE 8. The values of the transfer function
coefficients are shown in TABLE 3.
An inhibit input, regardless of its duration, does not affect the con-
verter update. A simple method of interfacing to a computer asyn-
chronously to CB is: (A) apply the inhibit, (B) wait 0.5 µs min., (C)
transfer the data and (D) release the inhibit.
14B
FIGURE 6. RESOLUTION CONTROL TIMING DIAGRAM
,,, ,,
0
µs
MIN
0.1
µs
MIN
5
Domestic Chip Exchange
京公网安备 11010802033920号
EEWORLD
