CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-65262B-9, HM-65262-9, HM-65262C-9 . . . . .-40
o
C to +85
o
C
DC Electrical Specifications
SYMBOL
ICCSB1
V
CC
= 5V
±10%;
T
A
= -40
o
C to +85
o
C (HM-65262B-9, HM-65262-9, HM-65262C-9)
LIMITS
PARAMETER
Standby Supply Current
MIN
-od
-
MAX
50
900
5
50
50
20
400
30
550
-
+1.0
+1.0
0.8
V
CC
+0.3
0.4
-
-
UNITS
µA
µA
mA
mA
mA
µA
µA
µA
µA
V
µA
µA
V
V
V
V
V
TEST CONDITIONS
HM-65262B-9, HM-65262-9, IO = 0mA,
E = V
CC
-0.3V, V
CC
= 5.5V
HM-65262C-9, IO = 0mA,
E = V
CC
-0.3V, V
CC
= 5.5V
E = 2.2V, IO = 0mA, V
CC
= 5.5V
E = 0.8V, IO = 0mA, V
CC
= 5.5V
E = 0.8V, IO = 0mA, f = 1MHz,
V
CC
= 5.5V
HM-65262B-9, HM-65262-9,
V
CC
= 2.0V, E = V
CC
HM-65262C-9, V
CC
= 2.0V, E = V
CC
HM-65262B-9, HM-65262-9,
V
CC
= 3.0V, E = V
CC
HM-65262C-9, V
CC
= 3.0V, E = V
CC
ICCSB
ICCEN
ICCOP
ICCDR
Standby Supply Current
Enabled Supply Current
Operating Supply Current (Note 1)
Data Retention Supply Current
-
-
-
-
-
ICCDR1
Data Retention Supply Current
-
-
VCCDR
II
IOZ
VIL
VIH
VOL
VOH1
VOH2
Data Retention Supply Voltage
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output High Voltage (Note 2)
T
A
= +25
o
C
PARAMETER
Input Capacitance (Note 2)
Input/Output Capacitance (Note 2)
2.0
-1.0
-1.0
-0.3
2.2
-
2.4
V
CC
-0.4
VI = V
CC
or GND, V
CC
= 5.5V
VIO = V
CC
or GND, V
CC
= 5.5V
V
CC
= 4.5V
V
CC
= 5.5V
IO = 8.0mA, V
CC
= 4.5V
IO = -4.0mA, V
CC
= 4.5V
IO = -100µA, V
CC
= 4.5V
Capacitance
SYMBOL
CI
CIO
NOTES:
MAX
10
12
UNITS
pF
pF
TEST CONDITIONS
f = 1MHz, All measurements are
referenced to device GND
1. Typical derating 5mA/MHz increase in ICCOP.
2. Tested at initial design and after major design changes.
6-3
HM-65262
AC Electrical Specifications
V
CC
= 5V
10%,T
A
= -40
o
C to +85
o
C (HM-65262B-9, HM-65262-9, HM-65262C-9)
LIMITS
HM-65262B-9
SYMBOL
READ CYCLE
(1)
(2)
(3)
(4)
(5)
(6)
(7)
TAVAX
TAVQV
TELQV
TELQX
Read/Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable Output Enable
Time
Chip Disable Output Hold
Time
Address Invalid Output Hold
Time
Chip Enable Output Disable
Time
70
-
-
5
5
5
-
-
70
70
-
-
-
30
85
-
-
5
5
5
-
-
85
85
-
-
-
30
85
-
-
5
5
5
-
-
85
85
-
-
-
30
ns
ns
ns
ns
ns
ns
ns
PARAMETER
MIN
MAX
HM-65262-9
MIN
MAX
HM-65262C-9
MIN
MAX
UNITS
TEST
CONDITIONS
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 2, 3)
TEHQX
TAXQX
TEHQZ
WRITE CYCLE
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
TAVAX
TELWH
TWLWH
TAVWL
TWHAX
TDVWH
TWHDX
TWLQZ
TWHQX
TAVWH
TAVEL
TEHAX
TAVEH
TELEH
TWLEH
TDVEH
TEHDX
Write Cycle Time
Chip Selection to End of
Write
Write Enable Pulse Width
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Write Enable Output Disable
Time
Write Disable Output Enable
Time
Address Valid to End of Write
Address Setup Time
Address Hold Time
Address Valid to End of Write
Enable Pulse Width
Write Enable Pulse Setup
Time
Chip Setup Time
Data Hold Time
70
55
40
0
0
30
0
-
0
55
0
0
55
55
40
30
0
-
-
-
-
-
-
-
30
-
-
-
-
-
-
-
-
-
85
65
45
0
0
35
0
-
0
65
0
0
65
65
45
35
0
-
-
-
-
-
-
-
30
-
-
-
-
-
-
-
-
-
85
65
45
0
0
35
0
-
0
65
0
0
65
65
45
35
0
-
-
-
-
-
-
-
30
-
-
-
-
-
-
-
0
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 2, 3)
(Notes 2, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
(Notes 1, 3)
NOTES:
1. Input pulse levels: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equivalent and C
L
= 50pF (min) - for C
L
greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. V
CC
= 4.5 and 5.5V.
6-4
HM-65262
Timing Waveforms
A
(3) TELQV
E
(7) TEHQZ
(4) TELQX
(5) TEHQX
Q
NOTE:
1. W is high for entire cycle and D is ignored. Address is stable by the time E goes low and remains valid until E goes high.
FIGURE 1. READ CYCLE 1: CONTROLLED BY E
(1) TAVAX
A
(2) TAVQV
E
(4) TELQX
(7) TEHQZ
(6) TAXQX
Q
NOTE:
1. W is high for the entire cycle and D is ignored. E is stable prior to A becoming valid and after A becomes invalid.
FIGURE 2. READ CYCLE 2: CONTROLLED BY ADDRESS
(8) TAVAX
A
(17) TAVWH
(9) TELWH
E
(11)
TAVWL
W
(12) TWHAX
(7) TEHQZ
(10) TWLWH
(13) TDVWH
D
(15) TWLQZ
(4)
TELQX
Q
(14) TWHDX
(16) TWHQX
NOTE:
1. In this mode, E rises after W. The address must remain stable whenever both E and W are low.
FIGURE 3. WRITE CYCLE 1: CONTROLLED BY W (LATE WRITE)
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