A
PPLICATION
N
OTES
A V A I L A B L E
AN3 • AN7 • AN8 • AN15 • AN16 • AN25 • AN29
• AN30 • AN35 • AN36 • AN39 • AN56 • AN69
X24C45
256 Bit
X24C45
Serial AUTOSTORE™ NOVRAM
16 x 16 Bit
FEATURES
DESCRIPTION
The Xicor X24C45 is a serial 256 bit NOVRAM featuring
a static RAM configured 16 x 16, overlaid bit-by-bit with
a nonvolatile E
2
PROM array. The X24C45 is fabricated
with Xicor’s Advanced CMOS Floating Gate technology.
The Xicor NOVRAM design allows data to be transferred
between the two memory arrays by means of software
commands or external hardware inputs. A store opera-
tion (RAM data to E
2
PROM) is completed in 5ms or less
and a recall operation (E
2
PROM data to RAM) is com-
pleted in 2µs or less.
The X24C45 also includes the AUTOSTORE feature, a
user selectable feature that automatically performs a
store operation when V
CC
falls below a preset threshold.
Xicor NOVRAMs are designed for unlimited write opera-
tions to RAM, either from the host or recalls from E
2
PROM
and a minimum 1,000,000 store operations. Inherent data
retention is specified to be greater than 100 years.
•
•
•
•
•
•
•
•
•
AUTOSTORE™ NOVRAM
—Automatically Performs a Store Operation
Upon Loss of V
CC
Single 5 Volt Supply
Ideal for use with Single Chip Microcomputers
—Minimum I/O Interface
—Serial Port Compatible (COPS™, 8051)
—Easily Interfaced to Microcontroller Ports
Software and Hardware Control of Nonvolatile
Functions
Auto Recall on Power-Up
TTL and CMOS Compatible
Low Power Dissipation
—Active Current: 10mA
—Standby Current: 50µA
8-Lead PDIP and 8-Lead SOIC Packages
High Reliability
—Store Cycles: 1,000,000
—Data Retention: 100 Years
FUNCTIONAL DIAGRAM
NONVOLATILE
2
E PROM
ST
O
R
E
ROW
DECODE
STATIC
RAM
256-BIT
EC
AL
L
CONTROL
LOGIC
R
RECALL (6)
AS (7)
CE (1)
DI (3)
SK (2)
INSTRUCTION
REGISTER
COLUMN
DECODE
DO (4)
INSTRUCTION
DECODE
4-BIT
COUNTER
3833 FHD F01
AUTOSTORE™ NOVRAM is a trademark of Xicor, Inc.
COPS is a trademark of National Semiconductor Corp.
© Xicor, Inc. 1991, 1995, 1996 Patents Pending
3833-1.5 2/24/99 T3/C3/D0 NS
1
Characteristics subject to change without notice
X24C45
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. CE must remain HIGH following a
Read or Write command until the data transfer is com-
plete. CE LOW places the X24C45 in the low power
standby mode and resets the instruction register. There-
fore, CE must be brought LOW after the completion of an
operation in order to reset the instruction register in
preparation for the next command.
Serial Clock (SK)
The Serial Clock input is used to clock all data into and
out of the device.
Data In (DI)
Data In is the serial data input.
Data Out (DO)
Data Out is the serial data output. It is in the high
impedance state except during data output cycles in
response to a READ instruction.
AUTOSTORE Output (AS)
AS
is an open drain output which, when asserted indi-
cates V
CC
has fallen below the AUTOSTORE threshold
(V
ASTH
).
AS
may be wire-ORed with multiple open drain
outputs and used as an interrupt input to a microcontroller
or as an input to a low power reset circuit.
RECALL
RECALL
LOW will initiate an internal transfer of data
from E
2
PROM to the RAM array.
PIN NAMES
Symbol
CE
SK
DI
DO
RECALL
AS
V
CC
V
SS
Description
Chip Enable
Serial Clock
Serial Data In
Serial Data Out
Recall Input
AUTOSTORE Output
+5V
Ground
3833 PGM T01
PIN CONFIGURATION
DIP/SOIC
CE
SK
DI
DO
1
2
3
4
X24C45
8
7
6
5
VCC
AS
RECALL
VSS
3833 FHD F02.1
2
X24C45
DEVICE OPERATION
The X24C45 contains an 8-bit instruction register. It is
accessed via the DI input, with data being clocked in on
the rising edge of SK. CE must be HIGH during the entire
data transfer operation.
Table 1. contains a list of the instructions and their
operation codes. The most significant bit (MSB) of all
instructions is a logic one (HIGH), bits 6 through 3 are
either RAM address bits (A) or don’t cares (X) and bits
2 through 0 are the operation codes. The X24C45
requires the instruction to be shifted in with the MSB first.
After CE is HIGH, the X24C45 will not begin to interpret
the data stream until a logic “1” has been shifted in on DI.
Therefore, CE may be brought HIGH with SK running
and DI LOW. DI must then go HIGH to indicate the start
condition of an instruction before the X24C45 will begin
any action.
In addition, the SK clock is totally static. The user can
completely stop the clock and data shifting will be
stopped. Restarting the clock will resume shifting of
data.
RCL and
RECALL
Either a software RCL instruction or a LOW on the
RECALL
input will initiate a transfer of E
2
PROM data
into RAM. This software or hardware recall operation
sets an internal “previous recall” latch. This latch is reset
upon power-up and must be intentionally set by the user
TABLE 1. INSTRUCTION SET
Instruction
WRDS (Figure 3)
STO (Figure 3)
ENAS
WRITE (Figure 2)
WREN (Figure 3)
RCL (Figure 3)
READ (Figure 1)
X = Don’t Care
A = Address
to enable any write or store operations. Although a recall
operation is performed upon power-up, the previous
recall latch is not set by this operation.
WRDS and WREN
Internally the X24C45 contains a “write enable” latch. This
latch must be set for either writes to the RAM or store
operations to the E
2
PROM. The WREN instruction sets
the latch and the WRDS instruction resets the latch,
disabling both RAM writes and E
2
PROM stores, effec-
tively protecting the nonvolatile data from corruption. The
write enable latch is automatically reset on power-up.
STO
The software STO instruction will initiate a transfer of
data from RAM to E
2
PROM. In order to safeguard
against unwanted store operations, the following condi-
tions must be true:
• STO instruction issued.
• The internal “write enable” latch must be set
(WREN instruction issued).
• The “previous recall” latch must be set (either a
software or hardware recall operation).
Once the store cycle is initiated, all other device func-
tions are inhibited. Upon completion of the store cycle,
the write enable latch is reset. Refer to Figure 4 for a
state diagram description of enabling/disabling condi-
tions for store operations.
Format, I
2
I
1
I
0
1XXXX000
1XXXX001
1XXXX010
1AAAA011
1XXXX100
1XXXX101
1AAAA11X
Operation
Reset Write Enable Latch (Disables Writes and Stores)
Store RAM Data in E
2
PROM
Enable AUTOSTORE Feature
Write Data into RAM Address AAAA
Set Write Enable Latch (Enables Writes and Stores)
Recall E
2
PROM Data into RAM
Read Data from RAM Address AAAA
3833 PGM T11
3
X24C45
WRITE
The WRITE instruction contains the 4-bit address of the
word to be written. The write instruction is immediately
followed by the 16-bit word to be written. CE must
remain HIGH during the entire operation. CE must go
LOW before the next rising edge of SK. If CE is brought
LOW prematurely (after the instruction but before 16 bits
of data are transferred), the instruction register will be
reset and the data that was shifted-in will be written to
RAM.
If CE is kept HIGH for more than 24 SK clock cycles (8-bit
instruction plus 16-bit data), the data already shifted-in will
be overwritten.
READ
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions, I
0
of the instruction word is a “don’t care”. This provides two
advantages. In a design that ties both DI and DO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an output
to an input. Secondly, it allows for valid data output
during the ninth SK clock cycle.
D0, the first bit output during a read operation, is trun-
cated. That is, it is internally clocked by the falling edge
of the eighth SK clock; whereas, all succeeding bits are
clocked by the rising edge of SK (refer to Read Cycle
Diagram).
LOW POWER MODE
When CE is LOW, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
AUTOSTORE Feature
The AUTOSTORE instruction (ENAS) sets the
“AUTOSTORE enable” latch, allowing the X24C45 to
automatically perform a store operation when V
CC
falls
below the AUTOSTORE threshold (V
ASTH
).
WRITE PROTECTION
The X24C45 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
Power-Up Condition
Upon power-up the “write enable” and “AUTOSTORE
enable” latches are in the reset state, disabling any store
operation.
Unknown Data Store
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hardware
recall operation, which assures that data in all RAM
locations is valid.
SYSTEM CONSIDERATIONS
Power-Up Recall
The X24C45 performs a power-up recall that transfers
the E
2
PROM contents to the RAM array. Although the
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X24C45 a
minimum of t
PUR
after V
CC
is stable.
4
X24C45
Figure 1. RAM Read
CE
SK
1
2
3
4
5
6
7
8
9
10
11
12
22
23
24
DI
1
A
A
A
A
1
1
X*
HIGH Z
DO
*Bit 8 of Read Instructions is Don’t Care
3833 FHD F09.1
D0
D1
D2
D3
D13
D14
D15
D0
Figure 2. RAM Write
CE
SK
1
2
3
4
5
6
7
8
9
10
11
21
22
23
24
DI
1
A
A
A
A
0
1
1
D0
D1
D2
D12
D13
D14
D15
3833 FHD F10.1
Figure 3. Non-Data Operations
CE
SK
1
2
3
4
5
6
7
8
DI
1
X
X
X
X
I
2
I
1
I
0
3833 FHD F11.1
5
京公网安备 11010802033920号
EEWORLD
