MCM69R618ZP5R datasheet, PDF - EEWORLD Datasheet

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MCM69R618ZP5R: Description64KX18 LATE-WRITE SRAM, 2.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119; Categorystorage storage; File Size379KB，20 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MCM69R618ZP5R Overview

64KX18 LATE-WRITE SRAM, 2.5ns, PBGA119, 14 X 22 MM, 1.27 MM PITCH, PLASTIC, BGA-119

MCM69R618ZP5R Parametric

Parameter Name	Attribute value
Maker	NXP
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	unknown
Maximum access time	2.5 ns
JESD-30 code	R-PBGA-B119
length	22 mm
memory density	1179648 bit
Memory IC Type	LATE-WRITE SRAM
memory width	18
Number of functions	1
Number of terminals	119
word count	65536 words
character code	64000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64KX18
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	BICMOS
Temperature level	COMMERCIAL
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
width	14 mm

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MOTOROLA

Freescale Semiconductor, Inc.

Order this document

by MCM69R536/D

SEMICONDUCTOR TECHNICAL DATA

Advance Information

1M Late Write HSTL

MCM69R536

MCM69R618

Freescale Semiconductor, Inc...

The MCM69R536/618 is a 1 megabit synchronous late write fast static RAM

designed to provide high performance in secondary cache, ATM switch,

Telecom, and other high speed memory applications. The MCM69R618

organized as 64K words by 18 bits, and the MCM69R536 organized as 32K

words by 36 bits wide are fabricated in Motorola’s high performance silicon gate

BiCMOS technology.

The differential CK clock inputs control the timing of read/write operations of

the RAM. At the rising edge of the CK clock all addresses, write enables, and

synchronous selects are registered. An internal buffer and special logic enable

the memory to accept write data on the rising edge of the CK clock a cycle after

address and control signals. Read data is driven on the rising edge of the CK

clock also.

The RAM uses HSTL inputs and outputs. The adjustable input trip – point (Vref)

and output voltage (VDDQ) gives the system designer greater flexibility in

optimizing system performance.

The synchronous write and byte enables allow writing to individual bytes or the

entire word.

The impedance of the output buffers is programmable allowing the outputs to

match the impedance of the circuit traces which reduces signal reflections.

ZP PACKAGE

PBGA

CASE 999–01

Byte Write Control

Single 3.3 V + 10%, – 5% Operation

JESD8–6 Class 1 Compatible)

HSTL – I/O (JEDEC Standard

HSTL – User Selectable

Input Trip–Point

HSTL – Compatible Programmable Impedance Output Drivers

Asynchronous Output Enable

Boundary Scan (JTAG) IEEE 1149.1 Compatible

Differential Clock Inputs

Optional x18 or x36 organization

MCM69R536/618–5 = 5 ns

MCM69R536/618–6 = 6 ns

MCM69R536/618–7 = 7 ns

MCM69R536/618–8 = 8 ns

•

119 Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Plastic Ball Grid Array

(PBGA) Package

•

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 1

8/15/97

Motorola, Inc. 1997

MOTOROLA FAST SRAM

For More Information On This Product,

Go to: www.freescale.com

MCM69R536•MCM69R618

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