K4D623237A
64M DDR SDRAM
64Mbit DDR SDRAM
512K x 32Bit x 4 Banks
Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and without DLL
Revision 1.2
February 2001
Samsung Electronics reserves the right to change products or specification without notice.
- 1 -
Rev. 1.2 (Feb. 2001)
K4D623237A
Revision History
Revision 1.2 (February 1, 2001)
• Corrected timing diaram on page 28,32.
• Removed K4D623237A-QC50
64M DDR SDRAM
Revision 1.1 (July 12, 2000)
• Removed Block Write function. Accordingly pin number 52 must be connected to low ( MCL only )
• Removed Write Interrupted by Read function.
• Changed I
CC1
/I
CC2N
/I
CC3N
/I
CC5
of K4D623237A-* in "DC Characteristics" table.
• Changed DC operating conditions
- V
REF
from 1.15V(min)/1.35V(max) to 0.49*V
DDQ
/0.51*V
DDQ
- V
IH
/V
IL
from V
REF
+0.18(min)/V
REF
-0.18(max) to V
REF
+0.15(min)
/
V
REF
-0.15(max)
Revision 1.0 (May 16, 2000)
• Changed tCDLR from 1CLK to 2CLK
• Changed tRPST from 0.9/1.1tCK to 0.4/0.5tCK
• Changed tAC(max) and tACS(max) of K4D623237A-QC70 from 5.5ns to 6.0ns
Revision 0.1 (April 24, 2000) -
Preliminary
• Changed tCDLR from 2CLK to 1CLK
Revision 0.0 (Februray 2, 2000) -
Target
• Defined Target Specification
- 2 -
Rev. 1.2 (Feb. 2001)
K4D623237A
64M DDR SDRAM
512K x 32Bit x 4 Banks Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and without DLL
FEATURES
• 3.3V
±5%
power supply for device operation
• 2.5V
±5%
power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive
going edge of the system clock
• Differential clock input
• Data I/O transactions on both edges of Data strobe
• Data input & output & DM are synchronized with DQS
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 16ms refresh period (2K cycle)
• 100pin TQFP package
• Maximum clock frequency up to 183MHz
• Maximum data rate up to 366Mbps/pin
ORDERING INFORMATION
Part NO.
K4D623237A-QC55
K4D623237A-QC60
K4D623237A-QC70
Max Freq.
183MHz
166MHz
143MHz
Max Data Rate
366Mbps/pin
333Mbps/pin
286Mbps/pin
SSTL_2
100 TQFP
Interface
Package
GENERAL DESCRIPTION
FOR 512K x 32Bit x 4 Bank DDR SDRAM
The K4D623237 is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 524,288 words by 32
bits, fabricated with SAMSUNG
′
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.5GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
- 3 -
Rev. 1.2 (Feb. 2001)
K4D623237A
PIN CONFIGURATION
(Top View)
64M DDR SDRAM
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
DQ29
VSSQ
DQ30
DQ31
VSS
VDDQ
N.C
N.C
N.C
N.C
N.C
VSSQ
RFU
DQS
VDDQ
VDD
DQ0
DQ1
VSSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
51
50
49
48
47
46
45
44
43
A8(AP)
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VREF
DQ28
DQ27
DQ26
DQ25
DQ24
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
MCL
VDD
DM3
DM1
DQ9
DQ8
CKE
VSS
CK
CK
A7
A6
A5
A4
VSS
A9
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
A10
VDD
A3
A2
A1
A0
100 Pin TQFP
20 x 14
mm
2
42
41
40
39
38
37
36
35
34
33
32
31
0.65mm pin Pitch
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM0
DM2
BA0
VSS
CAS
RAS
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
PIN DESCRIPTION
CK,CK
CKE
CS
RAS
CAS
WE
DQS
DM0 ~ DM3
RFU
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe
Data Mask
Reserved for Future Use
BA
0
, BA
1
A
0
~A
10
DQ
0
~ DQ
31
V
DD
V
SS
V
DDQ
V
SSQ
MCL
-
Bank Select Address
Address Input
Data Input/Output
Power
Ground
Power for DQ
′
s
Ground for DQ
′
s
Must Connect Low
-
VDDQ
VDD
- 4 -
Rev. 1.2 (Feb. 2001)
BA1
WE
CS
K4D623237A
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
CK,
CK
*1
Input
Type
Function
64M DDR SDRAM
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
′
s and DM
′
s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM
0
for DQ
0
~ DQ
7,
DM
1
for DQ
8
~ DQ
15,
DM
2
for
DQ
16
~ DQ
23,
DM
3
for DQ
24
~ DQ
31.
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
0
~ RA
10
, Column addresses : CA
0
~ CA
7
.
Column address CA
8
is used for auto precharge.
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
Must be connected low
CKE
Input
CS
Input
RAS
CAS
WE
DQS
DM
0
~ DM
3
DQ
0
~ DQ
31
BA
0
, BA
1
A
0
~ A
10
V
DD
/V
SS
V
DDQ
/V
SSQ
V
REF
MCL
Input
Input
Input
Input/Output
Input
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
MCL
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply V
REF
to CK pin.
- 5 -
Rev. 1.2 (Feb. 2001)
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