DATASHEET
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Description
The
9FG1901H
follows the Intel DB1900G Differential Buffer
Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock.
A differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1901. The
9FG1901H
can provide outputs up to 400MHz.
9FG1901H
Features/Benefits
•
•
•
•
•
•
•
•
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(18:17) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
VDDA controlled power down mode
Key Specifications
•
•
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew across all outputs in 1:1 mode < 150ps
Functional Block Diagram
OE_17_18#
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(18:17)
OE(16:5)#,
OE_01234#
13
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
STOP
LOGIC
17
DIF(16:0)
HIGH_BW#
FS_A_410
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT
TM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
1
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
SMB_A2_PLLBYP#
Pin Configuration
OE17_18#
CLK_IN#
DIF_18#
DIF_17#
DIF_16#
DIF_15#
DIF_14#
CLK_IN
DIF_18
DIF_17
DIF_16
DIF_15
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
IREF
GNDA
VDDA/PD#
HIGH_BW#
FS_A_410
DIF_0
DIF_0#
DIF_1
DIF_1#
1
2
3
4
5
6
7
8
9
54 OE14#
53 DIF_13#
52 DIF_13
51 OE13#
50 DIF_12#
49 DIF_12
48 OE12#
47 VDD
DIF_14
46 GND
45 DIF_11#
44 DIF_11
43 OE11#
42 DIF_10#
41 DIF_10
40 OE10#
39 DIF_9#
38 DIF_9
37 OE9#
SMB_A1
OE16#
GND 10
VDD 11
DIF_2 12
DIF_2# 13
DIF_3 14
DIF_3# 15
DIF_4 16
DIF_4# 17
OE_01234# 18
9FG1901
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SMBCLK
SMBDAT
OE5#
DIF_5
DIF_5#
OE6#
DIF_6
DIF_6#
VDD
GND
OE7#
DIF_7
DIF_7#
OE8#
DIF_8
DIF_8#
SMB_A0
72-pin MLF
Functionality at Power Up (PLL Mode)
FS_A_410
1
0
1
Power Groups
Pin Number
VDD
GND
3
2
11,27,47,63 10,28,46,64
Description
Main PLL, Analog
DIF clocks
CLK_IN
(CPU FSB)
MHz
100 <= CLK_IN < 200
200<= CLK_IN <= 400
DIF(18:0)
MHz
CLK_IN
CLK_IN
1. FS_A_410 is a low-threshold input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output
Parameters Table for correct values.
Power Down Functionality
INPUTS
OUTPUTS
PLL State
VDDA/PD# CLK_IN/CLK_IN# DIF DIF#
Running
3.3V (NOM)
Running
ON
Hi-Z
GND
X
OFF
Functionality Note
It is recommended that Byte 2, bit 6 be toggled from 1 to 0
and back to 1, the first time VDDA is applied. This ensures
proper initialization of the device.
IDT
TM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
2
OE15#
GND
VDD
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PIN NAME
IREF
GNDA
VDDA/PD#
HIGH_BW#
FS_A_410
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
DIF_2
DIF_2#
DIF_3
DIF_3#
DIF_4
DIF_4#
OE_01234#
SMBCLK
SMBDAT
OE5#
DIF_5
DIF_5#
OE6#
DIF_6
DIF_6#
VDD
GND
OE7#
DIF_7
DIF_7#
OE8#
DIF_8
DIF_8#
SMB_A0
SMB_A1
PIN TYPE
OUT
PWR
PWR
IN
IN
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
I/O
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
IN
DESCRIPTION
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in order
to establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core that also functions as Power Down. Collapsing
this power supply places the device in Power Down mode.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
3.3V tolerant low threshold input for CPU frequency selection. This pin
requires CK410 FSA. Refer to input electrical characteristics for Vil_FS and
Vih_FS threshold values.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pairs 0, 1, 2, 3 and 4.
1 = tri-state outputs, 0 = enable outputs
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
SMBus address bit 0 (LSB)
SMBus address bit 1
IDT
TM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
3
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Pin Description (continued)
PIN #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN NAME
OE9#
DIF_9
DIF_9#
OE10#
DIF_10
DIF_10#
OE11#
DIF_11
DIF_11#
GND
VDD
OE12#
DIF_12
DIF_12#
OE13#
DIF_13
DIF_13#
OE14#
DIF_14
DIF_14#
OE15#
DIF_15
DIF_15#
OE16#
DIF_16
DIF_16#
VDD
GND
DIF_17
DIF_17#
DIF_18
DIF_18#
OE17_18#
CLK_IN
CLK_IN#
SMB_A2_PLLBYP#
PIN TYPE
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
IN
IN
IN
DESCRIPTION
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 13.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 14.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 15.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 16.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pairs 17 and 18.
1 = tri-state outputs, 0 = enable outputs
True Input for differential reference clock.
Complement Input for differential reference clock.
SMBus address bit 2. When Low, the part operates as a fanout buffer with the
PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with
the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
1386A - 02/02/10
IDT
TM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
4
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
9FG1901 Programmable Gear Ratios
FS_A_410
SMBus
Byte 0
Bit 3
Bit 2
Bit 1
Bit 0
Input Output Gear Ratio
(m)
(n)
(n/m)
Input (CPU FSB) and Output
Frequencies (MHz)
200.0
3
5
12
2
5
8
3
4
6
1
5
4
3
2
3
1
1
2
5
1
3
5
2
3
5
1
6
5
4
3
5
2
0.333
0.400
0.417
0.500
0.600
0.625
0.667
0.750
0.833
1.000
1.200
1.250
1.333
1.500
1.667
2.000
266.7
320.0
333.3
400.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.7
88.9
106.7
111.1 133.3
80.0 106.7
128.0
133.3 160.0
83.3 111.1
133.3
138.9 166.7
100.0 133.3
160.0
166.7 200.0
120.0 160.0
192.0
200.0 240.0
125.0 166.7
200.0
208.3 250.0
133.3 177.8
213.3
222.2 266.7
150.0 200.0
240.0
250.0 300.0
166.7 222.2
266.7
277.8 333.3
200.0 266.7
320.0
333.3 400.0
240.0 320.0
384.0
400.0
NA
250.0 333.3
400.0
NA
NA
266.7 355.6
NA
NA
NA
300.0 400.0
NA
NA
NA
333.3
NA
NA
NA
NA
400.0
NA
NA
NA
NA
CLK IN (CPU FSB) Frequency (MHz)
100 133.33
160
166.67
1 0 0 0 0
3
1
0.333
1 0 0 0 1
5
2
0.400
NA
53.3
64.0
66.7
1 0 0 1 0
12
5
0.417
NA
55.6
66.7
69.4
1 0 0 1 1
2
1
0.500
50.0
66.7
80.0
83.3
1 0 1 0 0
5
3
0.600
60.0
80.0
96.0
100.0
1 0 1 0 1
8
5
0.625
62.5
83.3
100.0
104.2
1 0 1 1 0
3
2
0.667
66.7
88.9
106.7
111.1
1 0 1 1 1
5
4
0.800
80.0 106.7
128.0
133.3
1 1 0 0 0
6
5
0.833
NA
111.1
133.3
138.9
1
1
1.000
100.0 133.3
160.0
166.7
1 1 0 0 1
1 1 0 1 0
5
6
1.200
120.0 160.0
192.0
200.0
1 1 0 1 1
4
5
1.250
125.0 166.7
200.0
208.3
1 1 1 0 0
3
4
1.333
133.3 177.8
213.3
222.2
1 1 1 0 1
2
3
1.500
150.0 200.0
1 1 1 1 0
3
5
1.667
166.7 222.2
266.7
277.8
1 1 1 1 1
1
2
2.000
200.0 266.7
320.0
333.3
Note: Lines in
BOLD
are Power-up defaults for FS_A_410 = 0 and 1 respectively.
Shaded areas are shown for reference only and device operation is not guaranteed
IDT
TM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
5
京公网安备 11010802033920号
EEWORLD
