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9FG1901H

Description
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
File Size189KB,18 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
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9FG1901H Overview

Frequency Gearing Clock for CPU, PCIe Gen1 & FBD

DATASHEET
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Description
The
9FG1901H
follows the Intel DB1900G Differential Buffer
Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock.
A differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1901. The
9FG1901H
can provide outputs up to 400MHz.
9FG1901H
Features/Benefits
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(18:17) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
VDDA controlled power down mode
Key Specifications
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew across all outputs in 1:1 mode < 150ps
Functional Block Diagram
OE_17_18#
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(18:17)
OE(16:5)#,
OE_01234#
13
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
STOP
LOGIC
17
DIF(16:0)
HIGH_BW#
FS_A_410
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT
TM
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
1

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Description Frequency Gearing Clock for CPU, PCIe Gen1 & FBD Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
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