QL8050-7PV100C datasheet, PDF - EEWORLD Datasheet

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QL8050-7PV100C: DescriptionField Programmable Gate Array, 256 CLBs, 63840 Gates, CMOS, PQFP100, 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, MS-026D, VQFP-100; CategoryProgrammable logic devices Programmable logic; File Size440KB，49 Pages; ManufacturerQuickLogic Corporation; Websitehttps://www.quicklogic.com

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QL8050-7PV100C Overview

Field Programmable Gate Array, 256 CLBs, 63840 Gates, CMOS, PQFP100, 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, MS-026D, VQFP-100

QL8050-7PV100C Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	QuickLogic Corporation
Parts packaging code	QFP
package instruction	14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, MS-026D, VQFP-100
Contacts	100
Reach Compliance Code	compliant
Combined latency of CLB-Max	1.2838 ns
JESD-30 code	S-PQFP-G100
JESD-609 code	e0
length	14 mm
Humidity sensitivity level	3
Configurable number of logic blocks	256
Equivalent number of gates	63840
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature
organize	256 CLBS, 63840 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	TFQFP
Package shape	SQUARE
Package form	FLATPACK, THIN PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum supply voltage	1.89 V
Minimum supply voltage	1.71 V
Nominal supply voltage	1.8 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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0.18

µ,

six layer metal CMOS process

1.8 V Vcc, 1.8/2.5/3.3 V drive capable I/O

Up to 4,008 dedicated flip-flops

Up to 55.3 K embedded RAM Bits

Up to 313 I/O

Up to 370 K system gates

IEEE 1149.1 Boundary Scan Testing

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Multiple dedicated Low Skew Clock

Networks

High drive input-only networks

Quadrant-based segmentable clock networks

User Programmable Phase Locked Loops

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Hardwired DSP building blocks with integrated

Multiply, Add, and Accumulate Functions.

Compliant

Low Power Capability

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The QuickLogic products come with secure

ViaLink technology that protects intellectual

property from design theft and reverse

engineering. No external configuration memory

needed; Instant-on at Power-up.

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Up to twenty-four 2,304 bit Dual Port High

Performance SRAM Blocks

Up to 55,296 embedded RAM bits

RAM/ROM/FIFO Wizard for automatic

configuration

Configurable and cascadable

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High performance I/O cell with Tco< 3 ns

Programmable Slew Rate Control

Programmable I/O Standards:

LVTTL, LVCMOS, LVCMOS18, PCI,

PLL

Embedded RAM Blocks

Embeded Computational Units

PLL

GTL+, SSTL2, and SSTL3

Independent I/O Banks capable of

Fabric

supporting multiple standards in one device

I/O Register Configurations: Input,

PLL

Embedded RAM Blocks

PLL

Output, Output Enable (OE)

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WDATA

WADDR

RAM

Module

(2,304 bits)

RDATA

RADDR

WDATA

RAM

Module

(2,304 bits)

RDATA

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The RAM modules are dual-port, with completely independent READ and WRITE ports and

separate READ and WRITE clocks. The READ ports support asynchronous and synchronous

operation, while the WRITE ports support synchronous operation. Each port has 18 data lines

and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024

words. Depending on the mode selected, however, some higher order data or address lines may

not be used.

The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read

Enable (RE) acts as a clock enable for synchronous READ operation (ASYNCRD input low), or as

a flow-through enable for asynchronous READ operation (ASYNCRD input high).

Designers can cascade multiple RAM modules to increase the depth or width allowed in single

modules by connecting corresponding address lines together and dividing the words between

modules.

A similar technique can be used to create depths greater than 512 words. In this case address

signals higher than the ninth bit are encoded onto the write enable (WE) input for WRITE

operations. The READ data outputs are multiplexed together using encoded higher READ

address bits for the multiplexer SELECT signals.

The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO

functions) or with data from an external PROM (typically for ROM functions).

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Traditional Programmable Logic architectures do not implement arithmetic functions efficiently

or effectively—these functions require high logic cell usage while garnering only moderate

performance results.

The Eclipse-II architecture allows for functionality above and beyond that achievable using

programmable logic devices. By embedding a dynamically reconfigurable computational unit, the

Eclipse-II device can address various arithmetic functions efficiently. This approach offers greater

performance than traditional programmable logic implementations. The embedded block is

implemented at the transistor level as shown in

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