32 Megabit FLASH EEPROM
DP5Z1MW32PV3
DESCRIPTION:
The DP5Z1MW32PV3 ‘’VERSA-STACK’’ module is a memory subsystem
using DPAC Technologies’ ceramic Stackable Leadless Chip Carriers
(SLCC) mounted on a co-fired ceramic substrate. It offers 32 Megabits of
FLASH EEPROM in a single package envelope of 1.090" x 1.090" x .163".
The DP5Z1MW32PV3 is built with 2 SLCC packages each containing
1Meg x 16 FLASH memory devices. Each SLCC is hermetically sealed,
making the module suitable for commercial, industrial and military
applications.
By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a higher
board density of memory than available with conventional through-hole,
surface mount, module or hybrid techniques.
A0 - A19
PIN NAMES
Address Inputs
Data Input/Output
Chip Enables
Write Enables
Output Enables
Power (+5 Volts)
Ground
No Connect
I/O0 - I/O31
FEATURES:
•
Organizations Available:
•
Fast Access Times:
•
Single 5.0 Volt
•
High-Density Symmetrically Blocked Architecture
- Sixteen 128 Kbyte Blocks Per Device
•
Extended Cycling Capability
- 100K Write/Erase Cycles
•
Automated Erase and Program Cycles
- Command User Interface
- Status Register
•
SRAM-Compatible Write Interface
•
Hardware Data Protection Feature
- Erase / Write Lockout during
Power Transitions
•
66 - Pin PGA ‘’VERSA-STACK’’ Package
1 Meg x 32, 2 Meg x 16
CE0, CE1
WE
OE
V
DD
V
SS
N.C.
120, 150, 200ns (max.)
FUNCTIONAL BLOCK DIAGRAM
PIN-OUT DIAGRAM
30A180-11
Rev. D 5/02
This document contains information on a product that is currently released to production at DPAC Technologies Corp.
DPAC reserves the right to change products or specifications herein without prior notice.
1
32 Megabit FLASH EEPROM
DP5Z1MW32PV3
PIN NAMES
A0 - A19
I/O0 - I/O31
ADDRESS INPUTS: for memory address. Addresses are internally latched during a write cycle.
DATA INPUT/OUTPUT: Input data commands during Command Interface Register (CIR) write cycles.
Output array, status and identifier data in the appropriate read mode. Floats when the chip is de-selected
or the outputs are disabled.
CHIP ENABLES: Activate the device’s control logic, input buffers, decoders and sense amplifiers. With CE high, the
device is de-selected and per consumption reduces to Standby level upon completion of any current program or erase
operation. CE must be low to select the device. Device selection occurs with the falling edge of CE. The rising edge of
CE disables the device.
WRITE ENABLES: Controls writes to the Command Interface Register (CIR). WE is active low.
OUTPUT ENABLES: Gates the device’s data through the output buffers during a read cycle. OE is active low.
DEVICE POWER SUPPLY: (+5 Volts
±
10%)
GROUND
NO CONNECT
CE0, CE1
WE
OE
V
DD
V
SS
N.C.
BUS OPERATION
11
Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard
microprocessor bus cycles.
Table 1: Bus Operation
Mode
Read
1, 4
Output
Disable
1
Standby
1
Manufacturer Identifier
1, 3
Device Identifier
Write
1, 2
NOTES:
a. X can be V
IL
or V
IH
for address or control pins.
b. Command for different Erase operations, Data program operations can only be successfully completed through proper command sequence.
c.
V
ID
= 11.5V - 12.5V.
3
CE
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
OE
V
IL
V
IH
X
V
IL
V
IL
V
IH
WE
V
IH
V
IH
X
V
IH
V
IH
V
IL
A0
X
X
X
V
IL
V
IH
X
A1
X
X
X
V
IL
V
IL
X
A9
X
X
X
V
ID
V
ID
X
I/O0 - I/O7
(I/O16 - I/O23)
D
OUT
HIGH-Z
HIGH-Z
C2H
FAH/F1H
D
IN
12
I/O8 - I/O15
(I/O24 - I/O31)
HIGH-Z
HIGH-Z
HIGH-Z
00H
00H
D
IN
WRITE OPERATION
Commands are written to the COMMAND INTERFACE REGISTER
(CIR) using standard microprocessor write timing. The CIR serves
as the interface between the microprocessor and the internal chip
operation. The CIR can decipher Read Array, Read Silicon ID,
Erase and Program command. In the event of a read command,
the CIR simply points the read path at either the array or the Silicon
ID, depending on the specific read command given. for a program
or erase cycle, the CIR informs the write state machine that a
program or erase has been requested. During a program cycle, the
write state machine control the program sequences and the CIR will
only respond to status reads. During a sector/chip erase cycle, the
CIR will respond to status reads and erase suspend. After the write
state machine has completed its task, it will allow the CIR to
respond to its full command set. The CIR stays at read status
register mode until the microprocessor issues another valid
command sequence.
Device operations are selected by writing commands into the CIR.
Table 3 below defines 16 Megabit Flash family command.
30A180-11
Rev. D 5/02
www.dpactech.com
2
32 Megabit FLASH EEPROM
DP5Z1MW32PV3
DEVICE OPERATION
SILICON ID READ
The Silicon ID Read mode allows the reading out of a binary code
from the device and will identify its manufacturer and type. this is
intended for use by programming equipment for the purpose of
automatically matching the device to be programmed with its
corresponding programming algorithm. This mode is functional
over the entire temperature range of the device.
To activate the mode, the programming equipment must force V
ID
(11.5V ~ 12.5V) on address pin A9. Two identifier bytes may then
be sequenced from the device outputs by toggling address A0 from
V
IL
to V
IH
. All addresses are don’t cares except A0 and A1.
The manufacturer and device codes may also be read via the
command register, for instance when the device is erased or
programmed in a system without access to high voltage on the A9
pin. The command sequence is illustrated in Table 2.
To terminate the operation, it is necessary to write the read/reset
command sequence into the CIR.
READ RESET COMMAND
The read or reset operation is initiated by writing the read/reset
command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The device
remains enabled for reads until the CIR contents are altered by a
valid command sequence.
The device will automatically power-up in the read/reset state. In
this case, a command sequence is not required to read data. This
default value ensures that no spurious alteration of the memory
content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Table 2: Command Definition
11
Command
Sequence
Read/Reset
Silicon ID Read
Page/Byte Program
Chip Erase
Sector Erase
Erase Suspend
Erase Resume
Read Status
Register
Clear Status
Register
Sleep
Abort
First Bus
Bus
Write Cycle
Cycles
Req’d Address Date
Second Bus
Write Cycle
Address
Date
Third Bus
Write Cycle
Address
Date
Fourth Bus
Read/Write Cycle
Address
Date
Fifth Bus
Write Cycle
Address
Data
Sixth Bus
Write Cycle
Address
Data
4
4
4
6
6
3
3
4
3
3
3
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
AAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
55H
55H
55H
55H
55H
55H
55H
55H
55H
55H
55H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
5555H
F0H
90H
A0H
80H
80H
B0H
D0H
70H
50H
C0H
E0H
RA
00H/01H
PA
5555H
5555H
-
-
X
-
-
-
RD
C2H/FIH
PD
AAH
AAH
-
-
SRD
-
-
-
-
-
-
2AAAH
2AAAH
-
-
-
-
-
-
-
-
-
55H
55H
-
-
-
-
-
-
-
-
-
5555H
SA
-
-
-
-
-
-
-
-
-
10H
30H
-
-
-
-
-
-
NOTES:
Address bit A15 - A19 = X = Don’t Care for all address commands except for Programming Address (PA) and Sector Address (SA).
5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.
Bus operations are defined in Table 2.
RA = Address of the memory location to be read.
PA = Address of the memory to be programmed. Addresses are latched on the falling edge of the WE pulse.
SA = Address of the sector to be erased. The combination of A16 - A19 will be uniquely select any sector.
RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
SRD = Data read from Status Register.
Only I/O0 - I/O7 and I/O16 - I/O23 supplies command data, I/O8-I/O15 and I/O24-I/O31 = Don’t Care.
Table 3: Silicon ID Code
Type
Manufacturer’s
Code
Device Code
A19
X
X
A18
X
X
A17
X
X
A16
X
X
A1
V
IL
V
IL
A0
V
IL
V
IH
Code (HEX)
C2H
FAH/F1H
12
I/O7
1
1
I/O6
1
1
I/O5
0
1
I/O4
0
1
I/O3
0
0
I/O2
0
0
I/O1
1
0
I/O0
0
1
30A180-11
Rev. D 5/02
www.dpactech.com
3
32 Megabit FLASH EEPROM
DP5Z1MW32PV3
PAGE PROGRAM
To initiate Page Program mode, a three-cycle command sequence
is required. There are two “unlock” write cycles. These are
followed by writing the page program command - A0H.
After three-cycle command sequence is given, a word load is
performed by applying a low pulse on the WE or CE input with CE
or WE low (respectively) and OE high. The address is latched on
the falling edge of CE or WE, whichever occurs last. The data is
latched by the first rising edge of CE or WE. Maximum of 64 words
of data may be loaded into each page by the same procedures as
outlined in the page program section below.
Sector erase does not require the user to program the device prior
to erase. The system is not required to provide any controls or
timings during these operations.
The automatic sector erase begins on the rising edge of the last WE
pulse in the command sequence and terminates when the status on
I/O7 (I/O23) is “1" at which time the device stays at read status
register mode. The device remains enabled for read status register
mode until the CIR contents are altered by a valid command
sequence. (Refer to Tables 2, & 5 and Figures 3, 4, 6 & 8).
WORD LOAD
Word loads are used to enter the 64 words of a page to be
programmed. A word load is performed by applying a low pulse on
the WE or CE input CE or WE low respectively) and OE high. The
address is latched on the falling edge of CE or WE, whichever
occurs last. The data is latched by the first rising edge of CE or
WE.
A19
SA0
SA1
SA2
SA3
SA4
0
0
0
0
0
...
SA15
1
Table 4: Sector Address*
A18
0
0
0
0
1
....
1
A17
0
0
1
1
0
...
1
A16
0
1
0
1
0
...
1
Address Range
[A0 - A15]
00000H—0FFFFH
10000H—1FFFFH
20000H—2FFFFH
30000H—3FFFFH
40000H—4FFFFH
................
F0000H—FFFFFH
PROGRAM
Any page to be programmed should have the page in the erase
state first, i.e. performing sector erase is suggested before page
programming can be performed.
The device is programmed on a page basis. If a word of data within
a page is to be changed, data for the entire page can be loaded into
the device. Any word that is not loaded during the programming of
its page will be still in the erase state (i.e. FFFFH). Once the words
of a page are loaded into the device, they are simultaneously
programmed during the internal programming period. After the first
data word has been loaded into the device, successive words are
entered in the same manner. Each new word to be programmed
must have its high to low transition on WE (or CE) within 30µs of
the low to high transition of WE (or CE) of the preceding word. A6
to A19 specify the page address, i.e. the device is page-aligned on
64 word boundary The page address must be valid during each
high to low transition of WE or CE. A0 to A5 specify the word
address within the page. The word may be loaded in any order;
sequential loading is not required. If a high to low transition of CE
or WE is not detected within 100µs of the last low to high transition,
the load period will end and the internal programming period will
start. The auto page program terminates when status on I/O7 is “1"
at which time the device stays at read status register mode until the
CIR contents are altered by a valid command sequence. (Refer to
Table 2 & 5 and Figure 1, 6 & 7)
* Per 1 Meg x 16 device.
ERASE SUSPEND
This command only has meaning while the WSM is executing
SECTOR or CHIP erase operations, and therefore will only be
responded to during SECTOR or CHIP erase operation. After this
command has been executed, the CIR will initiate the WSM to
suspend erase operations, and then return to Read Status Register
mode. The WSM will set the I/O6 bit to a “1". Once the WSM has
reached the Suspend state, the WSM will set I/O7 (I/O23) bit to a
“1". At this time, WSM allows CIR to respond to the Read Array,
Read Status Register, Abort and Erase Resume commands only. In
this mode, the CIR will not respond to any other commands. the
WSM will continue to run, idling in the SUSPEND state, regardless
of the state of all input control pins.
ERASE RESUME
This command will cause the CIR to clear the suspend state and set
the I/O6 (I/O22) to a “0", but only in an Erase Suspend command
was previously used. Erase Resume will not have any effect in all
other conditions.
CHIP ERASE
Chip erase is a six-bus cycle operation. There are two “unlock”
write cycles. These are followed by writing the “set-up” command -
80H. Two more “unlock” write cycles are then followed by the chip
erase command - 10H.
Chip erase does not require the user to program the device prior to
erase.
The automatic erase begins on the rising edge of the last WE pulse
in the command sequence and terminates when the status on I/O7
(I/O23) is “1" at which time the device stays at read status register
mode until the CIR contents are altered by a valid command
sequence. (Refer to Tables 2 & 5 and Figures 2, 6 & 8).
READ STATUS REGISTER COMMAND
The module contains a Status Register which may be read to
determine when a program or erase operation is complete, and
whether that operation completed successfully. The status register
may be read at any time by writing the Read Status command to the
CIR. After writing this command, all subsequent read operations
output data from the status register, until another valid command is
written to the CIR. A Read Array command must be written to the
CIR to return to the Read Array mode.
The status register bits are output on I/O2 - I/O7 (I/O18 - I/O23)
(Table 5), I/O0 - I/O1 (I/O16 - I/O17) is set to 0H.
It should be noted that the status register are latched on the falling
edge of OE or CE whichever occurs last in the read cycle. This
prevents possible bus errors which might occur if the contents of the
status register change while reading the status register. CE or WE
must be toggled with each subsequent status read, or the
completion of a program or erase operation will not be evident.
SECTOR ERASE
Sector erase is a six-bus cycle operation. There are two “unlock”
write cycles. These are followed by writing the set-up command -
80H. Two more “unlock” write cycles are then followed by the
sector erase command - 30H. The sector address is latched on the
falling edge of WE, while the command (data) is latched on the
rising edge of WE.
30A180-11
Rev. D 5/02
www.dpactech.com
4
32 Megabit FLASH EEPROM
DP5Z1MW32PV3
The Status Register is the interface between the microprocessor
and the Write State Machine (WSM). When the WSM is active, this
register will indicate the status of the WSM, and will also hold the
bits indicating whether or not the WSM was successful in
performing the desired operation. The WSM sets status bits four
through seven and clears bits six and seven, but cannot clear status
bits four and five. If Erase fail or Program fail status bit is detected,
the Status Register is not cleared until the Clear Status Register
command is written. The device automatically outputs Status
Register data when read after Chip Erase, Sector Erase, Page
Program or Read Status Command write cycle. the default state of
the Status Register after power-up is (I/O7 - I/O4 and I/O23 - I/O20)
= 1000B. I/O3 and I/O19 = 0 or 1 depends on sector-protect status,
can not be changed by Clear Status Register Command or Write
State Machine. I/O2 and I/O16 = 0 or 1 depends on Sleep status,
During Sleep mode or Abort mode I/O2 (I/O18) is set to “1"; I/O2
(I/O18) is reset to ”0" by Read Array command.
command is written to the CIR. Then, any other command may be
issued to the CIR. Note again that before a read cycle can be
initiated, a Read command must be written to the CIR to specify
whether the read data is to come from the Array, Status Register or
Silicon ID.
SLEEP MODE
The device features two software controlled low-power modes:
Sleep and Abort modes. Sleep mode is allowable during any
current operations except that once Suspend command is issued,
Sleep command is ignored. Abort mode is executed only during
page Programming and Chip/Sector Erase mode.
To activate Sleep mode, a three-bus cycle operation is required.
C0H command (refer to Table 2) puts the device in the Sleep mode.
Once in the Sleep mode and CMOS input level applied, the power
of the device is reduced to deep power-down current levels. The
only threshold condition, input leakage, and output leakage.
The Sleep command allows the device to COMPLETE current
operations before going into Sleep mode. Once current operation is
done, device stays at read status register mode. The status
registers are not reset during sleep command. Program or Erase
fail bit may have been set if during program/erase mode the device
retry exceeds maximum count.
During Sleep mode, the status registers, Silicon ID codes remain
valid and can still be read. The device Sleep Status bit - I/O2
(I/O18) will indicate that the device in the sleep mode.
Write and Read Array command wakes up the device out of Sleep
mode, I/O2 (I/O18) is reset to “0" and device returns to standby
current level.
CLEAR STATUS REGISTER
The Erase fail status bit (I/O5 and I/O21) and Program fail status bit
(I/O4 and I/O20) are set by the write state machine, and can only
be reset by the system software. These bits can indicate various
failure conditions (see Table 5). By allowing the system software to
control the resetting of these bits, several operations may be
performed (such as cumulatively programming several pages or
erasing multiple blocks in sequence). The Status register may then
be read to determine if an error occurred during that programming
or erasing series. This adds flexibility to the way the device may be
programmed or erased. Additionally, once the program (erase) fail
bit happens, the program (erase) operation can not be performed
further. The program (erase) fail bit must be reset by system
software before further page program or sector (chip) erase are
attempted. To clear the status register, the Clear Status Register
Table 5: Status Register
11
STATUS
PROGRAM
a, b, f
IN PROGRESS
ERASE
a, c, f
I/O7
(I/O23)
0
0
0
1
1
1
1
1
1
I/O6
(I/O22)
0
0
1
1
0
0
0
0
0
I/O5
(I/O21)
0
0
0
0
0
0
0
1
0
I/O4
(I/O20)
0
0
0
0
0
0
1
0
0
I/O3
(I/O19)
1/01/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
I/O2
(I/O18)
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Note ‘g’
SUSPEND (NOT COMPLETE)
a, d, f
SUSPEND (COMPLETE)
a, d, f
PROGRAM
a, b, f
ERASE
a, c, f
PROGRAM
a, e, f
COMPLETE
FAIL
ERASE
a, e, f
AFTER CLEARING STATUS REGISTER
f
NOTES:
a. I/O7, I/O23: Write State Machine Status
1 = Ready, 0 = Busy
I/O6, I/O22: Erase Suspend Status
1 = Suspend, 0 = No Suspend
I/O5, I/O21: Erase Fail Status
1 = Fail in Erase, 0 = Successful Erase
I/O4, I/O20: Program Fail Status
1 = Fail in Program, 0 = Successful Program
I/O3, I/O19: Sector-Protect Status (Not Used)
I/O2, I/O18: Sleep Status
1 = Device in Sleep Status, 0 = Device Not in Sleep Status
I/O1-I/O0, I/O17-I/O16 = Reserved for further enhancements.
These bits are reserved for future use; mask them out when polling
the Status Register.
30A180-11
Rev. D 5/02
b. Program Status is for the status during Page Programming mode.
c. Erase Status is for the status during Sector/Chip Erase mode.
d. Suspend Status is for both Sector and Chip Erase mode.
e. Fail Status bit (I/O4, I/O20 or I/O5,I/O21) is provided during Page
Program or Sector/Chip Erase modes respectively.
f. I/O2, I/O18 = 0 or 1 depends on whether device is in the Sleep
mode or not.
g. Once in the Sleep mode, I/O2, I/O18 is set to “1", and is reset by
read array command only.
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