8 Megabit FLASH EEPROM
DPZ1MM8NY/NI3/NH3/NJ3/DPZ1MX8NA3
DESCRIPTION:
The DPZ1MM8NY/NI3/NH3/NJ3/DPZ1MX8NA3 ‘’SLCC’’ devices are a
revolutionary new memory subsystem using Dense-Pac Microsystems’
ceramic Stackable Leadless Chip Carriers (SLCC). Available unleaded,
straight leaded, ‘’J’’ leaded, gullwing leaded packages, or mounted on a
50-pin PGA co-fired ceramic substrate. The Device packs 8-Megabits of
2
FLASH EEPROM in an area as small as 0.463 in , while maintaining a total
height as low as 0.110 inches.
The DPZ1MM8NY/NI3/NH3/NJ3/DPZ1MX8NA3 is a 1 Meg x 8 FLASH
EEPROM memory devices. Each SLCC is hermetically sealed making the
module suitable for commercial, industrial and military applications.
By using SLCCs, the ‘’Stack’’ family of modules offer a higher board density
of memory than available with conventional through-hole, surface mount
or hybrid techniques.
DPZ1MM8NY
FEATURES:
•
Organization: 1 Meg x 8
•
Fast Access Times: 90, 100, 120, 150ns (max.)
•
High-Density symmetrically Blocked Architecture
- Sixteen 64 Kbyte Blocks Per Device
•
Extended Cycling Capability
- 10K Block Erase Cycles
•
Automated Byte Write and Block Erase
- Command User Interface
- Status Register
•
SRAM-Compatible Write Interface
•
Hardware Data Protection Feature
- Erase / Write Lockout during
Power Transitions
•
Packages Available:
DPZ1MM8NY
48 - Pin SLCC
DPZ1MM8NI3
48 - Pin Straight Leaded SLCC
DPZ1MM8NH3
48 - Pin Gullwing Leaded SLCC
DPZ1MM8NJ3
48 - Pin ‘’J’’ Leaded SLCC
DPZ1MX8NA3
50 - Pin PGA Dense-SLCC
DPZ1MM8NI3
DPZ1MM8NJ3
DPZ1MX8NA3
DPZ1MM8NH3
30A117-01
REV. C
This document contains information on a product presently under
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
1
DPZ1MM8NY/NI3/NH3/NJ3/DPZ1MX8NA3
Dense-Pac Microsystems, Inc.
PIN NAMES
A0 - A19
I/O0 - I/O7
CE
WE
OE
V
PP
V
DD
V
SS
N.C.
Address Inputs
Data Input/Output
Chip Enable
Write Enable
Output Enable
Programming Voltage
(+12.0V)
Power (+5V)
Ground
No Connect
FUNCTIONAL BLOCK DIAGRAM
PIN-OUT DIAGRAM
48 - PIN LEADLESS SLCC
48 - PIN STRAIGHT LEADED SLCC
48 - PIN ‘’J’’ LEADED SLCC
48 - PIN GULLWING LEADED SLCC
50 - PIN PGA
DENSE-STACK
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Dense-Pac Microsystems, Inc.
DPZ1MM8NY/NI3/NH3/NJ3/DPZ1MX8NA3
again possible via the Read Array command. Erase
suspend/resume capability allows system software to suspend
block erase to read data and execute code from any other block.
voltage range 4.5V to 5.5V.
When the CE pin is at V
DD
, the I
CC
CMOS Standby mode is
enabled.
PRINCIPLES OF OPERATION
The is a high-performance 8 Megabit memory organized as 1
Mbyte (1,048,576 bytes) of 8 bits each. A 64 Kbyte (65,536 byte)
block is included in a single 1 Meg x 8 devices. A memory map
is shown in this specification. A block erase operation erases one
of the sixteen blocks of memory in typically 1.6 seconds,
independent of the remaining blocks. Each block can be
independently erased and written 10,000 cycles. Erase Suspend
mode allows system software to suspend block erase to read data
or execute code from any other block of each device.
The Command User Interface serves as the interface between the
microprocessor or microcontroller and the internal operation of
the fuse devices.
Byte Write and Block Erase Automation allow byte write and
block erase operations to be executed using a two-write command
sequence to the Command User Interface. The internal Write
State Machine (WSM) automatically executes the algorithms and
timings necessary for byte write and block erase operations,
including verifications, thereby unburdening the microprocessor
or microcontroller. Writing of memory data is performed in byte
increments typically within 9µs, an 80% improvement over
current flash memory products.
The Status Register indicates the status of the WSM and when the
WSM successfully completes the desired byte write or block erase
operation.
Maximum access time is 150ns (t
ACC
) over the military
temperature range (-55
o
C to +125
o
C) and over V
DD
supply
PRODUCT OVERVIEW
COMMAND USER INTERFACE AND WRITE
AUTOMATION
An on-chip state machine controls block erase and byte write,
freeing the system processor for other tasks. After receiving the
Erase Setup and Erase Confirm commands, the state machine
controls block pre-conditioning and erase, returning progress via
the status Register. Byte write is similarly controlled, after
destination address and expected data are supplied. The program
and erase algorithms are regulated by the state machine, including
pulse repetition where required and internal verification and
margining of data.
DATA PROTECTION
Depending on the application, the system designer may choose
to make the V
PP
power supply switchable (available only when
memory byte writes/block erases are required) or hardwired to
V
PPH
.
When V
PP
= V
PPL
, memory contents cannot be altered. The
module Command User Interface architecture provides
protection from unwanted byte write or block erase operations
even when high voltage is applied to V
PP
. Additionally, all
functions are disabled whenever V
DD
is below the write lockout
voltage V
LKO
.
The module accommodates either design practice
and encourage optimization of the processor-memory interface.
The two-step byte write/block erase Command User Interface
write sequence provides additional software write protection.
MEMORY MAP *
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
64 Kbyte Block
* Per 1 Meg x 8 Device.
enable successful block erasure and byte writing of the
device. All functions associated with altering memory
contents (byte write, block erase, status and device identifier)
are accessed via the Command User Interface and verified
through the Status Register.
Commands are written using standard microprocessor write
timings. Command User Interface contents serve as input to the
WSM, which controls the block erase and byte write circuitry.
Write cycles also internally latch addresses and data needed for
byte write or block erase operations. With the appropriate
command written to the register, standard microprocessor read
timings output array data, access the device identifier codes, or
output byte write and block erase status for verification.
Interface software to initiate and poll progress of internal byte
write and block erase can be stored in any of the module blocks.
This code is copied to, and executed from, system RAM during
actual flash memory update. After successful completion of byte
write and/or block erase, code/data reads from the module are
30A117-01
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The device includes on-chip write automation to manage write
and erase functions. The Write State Machine allows for: 100%
TTL-level control inputs, fixed power supplies during block
erasure and byte write, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up, or after return from deep
powerdown mode (see Table 1), the module functions as a
read-only memory. Manipulation of external memory-control
pins allow array read, standby and output disable operations.
Both Status Register and device identifier can also be accessed
through the Command User Interface when V
PP
= V
PPL
.
This same subset of operations is also available when high voltage
is applied to the V
PP
pin. In addition, high voltage on V
PP
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DPZ1MM8NY/NI3/NH3/NJ3/DPZ1MX8NA3
BUS OPERATION
Flash memory reads, erases and writes in-system via the local
CPU. All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
Dense-Pac Microsystems, Inc.
CPU can then automatically match the device with its proper
block erase and byte write algorithms.
The manufacture and device codes are read via the Command
User Interface. Following a write of 90H to the Command User
Interface, a read from address location 00000H outputs the
manufacturer code (89H). A read from address location 00001H
outputs the device code (A2H). It is not necessary to have high
voltage applied to V
PP
to read the device identifier from the
Command User Interface.
READ
The module has three read modes. The memory can be read from
any of its blocks, and information can be read from the device
identifier or Status Register. V
PP
can be at either V
PPL
or V
PPH
.
The first task is to write the appropriate read mode command to
the Command User Interface (array, device identifier, or Status
Register). The module automatically resets to Read Array mode
upon initial device powerup. The module has four control pins,
two of which must be logically active to obtain data at the outputs.
Chip Enable (
CE
) is the device selection control, and when active
enables the selected memory device. Output Enable (OE) is the
data input/output (I/O0 - I/O7) direction control, and when active
derives data from the selected memory onto the I/O bus. The AC
Waveform for Read Operations illustrates read bus cycle
waveforms.
WRITE
Writes to the Command User Interface enable reading of device
data and device identifier. They also control inspection and
clearing of the Status Register. Additionally, when V
PP
= V
PPH
,
the Command User Interface controls block erasure and byte
write. The contents of the interface register serve as input to the
internal write state machine.
The Command User Interface itself does not occupy an
addressable memory location. The interface register is a latch
used to store the command and address and data information
needed to execute the command. Erase Setup and Erase Confirm
commands require both appropriate command data and an
address within the block to be erased. The Byte Write Setup
command requires both appropriate command data and the
address of the location to be written.
The Command User Interface is written by bringing WE to a
logic-low level (V
IL
) while
CE
is low. Addresses and data are
latched on the rising edge of WE. Standard microprocessor write
timing are used.
Refer to AC Write Characteristics and the AC Waveforms for Write
Operations, for specific timing parameters.
OUTPUT DISABLE
With OE at a logic-high level (V
IH
), the device outputs are
disabled. Output pins (I/O0 - I/O7) are placed in a
high-impedance state.
STANDBY
CE at a logic-high level (V
IH
) places the module in standby mode.
Standby operation disables much of the modules circuitry and
substantially reduces device power consumption. The outputs
(I/O0 - I/O7) are placed in a high- impedance state independent
of the status of OE. If each device is deselected during block erase
or byte write, the device will continue functioning and consuming
normal active power until the operation completes.
DEVICE IDENTIFIER OPERATION
The device identifier operation outputs the manufacturer code,
89H, and the device code, A2H, for each device. The system
Table 1: BUS OPERATION
Mode
Read
1, 2
CE
V
IL
V
IL
V
IH
V
IL
V
IL
V
IL
OE
V
IL
V
IH
X
V
IL
V
IL
V
IH
WE
V
IH
V
IH
X
V
IH
V
IH
V
IL
A0
X
X
X
V
IL
V
IH
X
V
PP
X
X
X
X
X
X
I/O0-I/O7
D
OUT
HIGH-Z
HIGH-Z
89H
A2H
D
IN
Output Disable
Standby
Device Identifier (Mfg.)
Device Identifier (Device)
Write
NOTES:
1.
2.
3.
4.
3, 4
Refer to DC Characteristics. When V
PP
= V
PPL
, memory contents can be read but not written or erased.
X can be V
IL
or V
IH
for control pins and addresses, and V
PPH
for V
PP
. See DC Characteristics for V
PPL
= V
PPL
voltages.
Command writes involving block erase or byte write are only successfully executed when V
PP
= V
PPH
.
Refer to Command Definitions for valid D
IN
during a write operation.
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30A117-01
REV. C
Dense-Pac Microsystems, Inc.
DPZ1MM8NY/NI3/NH3/NJ3/DPZ1MX8NA3
from the Status Register, until another valid command is written
to the Command User Interface. The contents of the Status
Register are latched on the falling edge of OE or CE, whichever
occurs last in the read cycle. OE or
CE
must be toggled to V
IH
before further reads to update the Status Register latch. The Read
Status Register command functions when V
PP
= V
PPL
or V
PPH
.
COMMAND DEFINITIONS
When V
PPL
is applied to the V
PP
pin, read operations from the
Status Register, device identifier, or array blocks are enabled.
Placing V
PPH
on V
PP
enables successful byte write and block erase
operations as well.
Device operations are selected by writing specific commands into
the Command User Interface. Table 2 defines the device.
CLEAR STATUS REGISTER COMMAND
The Erase Status and Byte Write Status bits are set to “1”s by the
Write State Machine and can only be reset by the Clear Status
Register Command. These bits indicate various failure conditions
(see Table 3). By allowing system software to control the resetting
of these bits, several operations may be performed (such as
cumulatively writing several bytes or erasing multiple blocks in
sequence). The Status Register may then be polled to determine
if an error occurred during that sequence. This adds flexibility to
the way the device may be used.
Additionally, the V
PP
Status bit (SR.3) MUST be reset by system
software before further byte writes or block erase are attempted.
To clear the Status Register, the Clear Status Register command
(50H) is written to the Command User Interface. The Clear Status
Register command is functional when V
PP
= V
PPL
or V
PPH
.
READ ARRAY COMMAND
Upon initial device powerup the module defaults to Read Array
mode. This operation is also initiated by writing FFH into the
Command User Interface. Microprocessor read cycles retrieve
array data. The device remains enabled for reads until the
Command User Interface contents are altered. Once the internal
Write State Machine has started a block erase or byte write
operation, the device will not recognize the Read Array
command, until the WSM has completed it s operation. The Read
Array command is functional when V
PP
= V
PPL
or V
PPH
.
DEVICE IDENTIFIER COMMAND
Each device contains a device identifier operation, initiated by
writing 90H into the Command User Interface. Following the
command write, a read cycle form address 00000H retrieves the
manufacturer code of 89H. A read cycle form address 000001H
returns, the device code of A2H. To terminate the operation, it
is necessary to write another valid command into the register.
Like the Read Array command, the device identifier command is
functional when V
PP
= V
PPL
or V
PPH
.
ERASE SETUP / ERASE CONFIRM COMMANDS
Erase is executed one block at a time, initiated a two-cycle
command sequence. An Erase Setup command (20H) is first
written to the Command User Interface, followed by the Erase
Confirm command (D0H). These commands require both
appropriate sequencing and an address within the block to be
erased to FFH. Block preconditioning, erase and verify are all
handled internally by the Write State Machine, invisible to the
system. After the two-command erase sequence is written to it,
the device automatically outputs Status Register data when read
(see Figure 3; Block Erase Flowchart). The CPU can detect the
completion of the erase event by analyzing the WSM Status bit of
the Status Register.
READ STATUS REGISTER COMMAND
The module contains a Status Register which may be read to
determine when a byte write or block erase operation is complete,
and whether that operation completed successfully. The Status
Register may be read at any time by writing the Read Status
Register command (70H) to the Command User Interface. After
writing this command, all subsequent read operations output data
Table 2: COMMAND DEFINITION
Command
Read Array/Reset
device Identifier
Read Status Register
Clear Status Register
Erase Setup/Erase Confirm
Erase Suspend/Erase Resume
Byte Write Setup/Write
Alternate Byte Write
Setup/Write
Bus
Cycles
Req’d
1
3
2
1
2
2
2
2
First Bus Cycle
Operation
Address
Data
1
Operation
Second Bus Cycle
Address
Data
1
Write
Write
Write
Write
Write
Write
Write
Write
X
X
X
X
BA
X
WA
WA
FFH
90H
70H
50H
20H
B0H
40H
10H
-
Read
Read
-
Write
Write
Write
Write
-
DA
X
-
BA
X
WA
WA
-
DID
SRD
-
D0H
D0H
WD
WD
BA = Address within the block being erased.
DA = Device Address: 00H for manufacturer code, 01H for device code.
DID = Data read from device identifiers.
SRD = Data read from Status Register (see Table 3).
WA = Address of memory location to be written.
WD = Data to be written at location WA. Data is latched on the
rising edge of WE.
NOTES:
1.
2.
3.
4.
Bus operations are defined in Table 2.
Following the device identifier command, two read operations access manufacturer and device codes.
Either 40H or 10H are recognized by WSM as the Byte Write Setup command.
Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
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