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FTS88130-55C6MB

Description
Standard SRAM, 128KX8, 55ns, CMOS, CDIP32, 0.600 INCH, CERAMIC PACKAGE-32
Categorystorage    storage   
File Size1MB,15 Pages
ManufacturerForce Technologies Ltd.
Download Datasheet Parametric View All

FTS88130-55C6MB Overview

Standard SRAM, 128KX8, 55ns, CMOS, CDIP32, 0.600 INCH, CERAMIC PACKAGE-32

FTS88130-55C6MB Parametric

Parameter NameAttribute value
MakerForce Technologies Ltd.
Parts packaging codeDIP
package instructionDIP,
Contacts32
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time55 ns
JESD-30 codeR-CDIP-T32
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize128KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
Parallel/SerialPARALLEL
Certification statusNot Qualified
Filter levelMIL-STD-883
Maximum seat height5.715 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
128Kx8 High Speed SRAM
FTS88130
FEATURES
High Speed (Equal Access and Cycle Times)
— 15/20/25/35 ns (Commercial)
— 20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70/85/100/120 ns (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
—32-Pin 600 mil Ceramic DIP
—32-Pin 400 mil Ceramic DIP
—32-Pin Solder Seal Flatpack
—32-Pin LCC (400 x
820
mil)
[Two-Sided]
—32-Pin Ceramic SOJ
DESCRIPTION
The
FT88130
is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The
FTS88130
is a member of a family of
FT SRAM
products offer-
ing fast access times.
The
FTS88130
device provides asynchronous opera-
tions with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
.
Reading is accomplished by device selection (CE
1
low
and CE
2
high) and output enabling (OE) while write
enable (WE) remains HIGH. By presenting the ad-
dress under these conditions, the data in the ad-
dressed memory location is presented on the data
input/output pins. The input/output pins stay in the
HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P300, C10, C11),
SOJ (J300, J400, CJ),
SOLDER SEAL
FLATPACK (FS-3) SIMILAR
LCC (L6)
1
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