54F377DM datasheet, PDF - EEWORLD Datasheet

54F377DM: DescriptionOctal D Flip-Flop with Clock Enable; Categorylogic logic; File Size142KB，8 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

Stay tuned Parametric Compare

54F377DM Overview

Octal D Flip-Flop with Clock Enable

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DIP, DIP20,.3
Reach Compliance Code	unknow
Other features	WITH HOLD MODE
series	F/FAST
JESD-30 code	R-GDIP-T20
JESD-609 code	e0
length	24.51 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	D FLIP-FLOP
Number of digits	8
Number of functions	1
Number of terminals	20
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Output polarity	TRUE
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP20,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Maximum supply current (ICC)	56 mA
propagation delay (tpd)	10.5 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	POSITIVE EDGE
width	7.62 mm
minfmax	85 MHz
Base Number Matches	1

	54F377DM	54F377FM	54F377LM	74F377PC	74F377SC	74F377SJ
Description	Octal D Flip-Flop with Clock Enable	Octal D Flip-Flop with Clock Enable	Octal D Flip-Flop with Clock Enable	Octal D Flip-Flop with Clock Enable	Octal D Flip-Flop with Clock Enable	Octal D Flip-Flop with Clock Enable

The world's first Japanese Lexus ES will be equipped with electronic exterior mirrors: Recently, Lexus officially announced that it will provide electronic exterior mirrors for the new generation Lexus ES in Japan. Lexus ES has become the world's first mass-produced model equipped with ...; tlyl18108837711 Integrated technical exchanges

How to write a 32-bit array into FIFO in 8-bit increments?: I want to write a 32-bit array into FIFO, but I can only write 8 bits at a time, which means it needs 4 clock cycles. However, I get an error every time I program. Here is my program idea, which is a ...; hms2006 FPGA/CPLD

SPI frequency: What is the frequency range supported by SPI?...; l0700830216 Microcontroller MCU

TI's product pins have copper leakage: Please help, we bought a batch of 17+ year products. After testing, QC said that the pins were seriously leaking copper and could not be used, so we asked for a return. The supplier said that this was...; 萌新采购 TI Technology Forum

FPGA module parameterized design method: Please throw bricks!...; eeleader FPGA/CPLD

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components