Latch-up Current...................................................... >200 mA
Operating Range
Device
CY62146DV30L
CY62146DV30LL
Range
Ambient Tem-
perature (T
A
)
V
CC
[8]
Industrial –40°C to +85°C 2.20V to 3.60V
Electrical Characteristics
Over the Operating Range
CY62146DV30-45
Parameter Description
V
OH
V
OL
V
IH
Test Conditions
Min. Typ.
[5]
2.0
2.4
0.4
0.4
1.8
2.2
–0.3
–0.3
–1
–1
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+1
+1
1.8
2.2
–0.3
–0.3
–1
–1
Max.
Output HIGH I
OH
= –0.1 mA V
CC
= 2.20V
Voltage
I
OH
= –1.0 mA V
CC
= 2.70V
Output LOW I
OL
= 0.1 mA V
CC
= 2.20V
Voltage
I
OL
= 2.1 mA V
CC
= 2.70V
Input HIGH
Voltage
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
V
IL
I
IX
I
OZ
I
CC
Input LOW
Voltage
V
CC
= 2.2V to 2.7V
V
CC
= 2.7V to 3.6V
CY62146DV30-55
Min. Typ.
[5]
2.0
2.4
0.4
0.4
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+1
+1
1.8
2.2
–0.3
–0.3
–1
–1
Max.
CY62146DV30-70
Min. Typ.
[5]
Max. Unit
2.0
2.4
0.4
0.4
V
CC
+
0.3V
V
CC
+
0.3V
0.6
0.8
+1
+1
V
V
V
V
V
V
V
V
µA
µA
Input Leakage GND < V
I
< V
CC
Current
Output
Leakage
Current
V
CC
Operating
Supply
Current
Automatic
CE
Power-down
Current —
CMOS
Inputs
GND < V
O
< V
CC
, Output
Disabled
f = f
MAX
=
1/t
RC
f = 1 MHz
V
CC
= V
CCmax
I
OUT
= 0 mA
CMOS levels
10
1.5
2
20
3
12
8
8
1.5
2
15
3
12
8
8
1.5
2
15
3
12
8
mA
mA
µA
I
SB1
CE > V
CC
−0.2V,
L
V
IN
>V
CC
–0.2V, V
IN
<0.2V) LL
f = f
MAX
(Address and Data
Only),
f = 0 (OE, WE, BHE and
BLE), V
CC
= 3.60V
I
SB2
CE > V
CC
– 0.2V,
Automatic
L
CE
V
IN
> V
CC
– 0.2V or V
IN
< LL
Power-down 0.2V,
Current —
f = 0, V
CC
= 3.60V
CMOS Inputs
2
12
8
2
12
8
2
12
8
µA
Notes:
6. V
IL(min.)
= –2.0V for pulse durations less than 20 ns.
7. V
IH(max)
= V
CC
+0.75V for pulse durations less than 20 ns.
8. Full device AC operation assumes a 100-µs ramp time from 0 to V
CC
(min) and 200
µs
wait time after V
CC
stabilization.
Document #: 38-05339 Rev. *A
Page 3 of 11
[+] Feedback
CY62146DV30
Capacitance
(for all packages)
[9]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max.
10
10
Unit
pF
pF
Thermal Resistance
[9]
Parameter
Θ
JA
Θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, four-layer
printed circuit board
BGA
72
8.86
TSOP II
75.13
8.95
Unit
°C/W
°C/W
AC Test Loads and Waveforms
[10]
V
CC
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R1
V
CC
R2
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
THÉ
VENIN EQUIVALENT
R
TH
OUTPUT
V
3.0V
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
2.50V
16667
15385
8000
1.20
Data Retention Characteristics
(Over the Operating Range)
Parameter
V
DR
I
CCDR
Description
V
CC
for Data Retention
Data Retention Current
V
CC
= 1.5V
CE > V
CC
– 0.2V,
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V
L
LL
0
t
RC
Conditions
Min.
1.5
9
6
ns
ns
Typ.
[5]
Max.
Unit
V
µA
t
CDR[9]
t
R[11]
Chip Deselect to Data Retention Time
Operation Recovery Time
Data Retention Waveform
V
CC
CE
V
CC(min)
t
CDR
DATA RETENTION MODE
V
DR
> 1.5 V
V
CC(min)
t
R
Notes:
9. Tested initially and after any design or process changes that may affect these parameters.
10. Test condition for the 45 ns part is a load capacitance of 30 pF.
11. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs
or stable at V
CC(min.)
> 100
µs.
Document #: 38-05339 Rev. *A
Page 4 of 11
[+] Feedback
CY62146DV30
Switching Characteristics
Over the Operating Range
[12]
45 ns
[10]
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
[15]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z
[13, 14]
WE HIGH to Low-Z
[13]
10
45
40
40
0
0
35
40
25
0
15
10
55
40
40
0
0
40
40
25
0
20
10
70
60
60
0
0
45
60
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to LOW Z
[13]
OE HIGH to High Z
[13, 14]
CE LOW to Low Z
[13]
CE HIGH to High Z
[13, 14]
CE LOW to Power-Up
CE HIGH to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[13]
BLE/BHE HIGH to HIGH Z
[13, 14]
10
15
0
45
25
10
20
10
20
0
55
25
10
25
5
15
10
20
0
70
35
10
45
25
5
20
10
25
45
45
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
55 ns
Max.
Min.
70 ns
Max.
Unit
Notes:
12. Test conditions for all parameters other than three-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of V
CC(typ)
/2,
input pulse levels of 0 to V
CC(typ.)
, and output loading of the specified I
OL
/I
OH
as shown in the “AC Test Loads and Waveforms” section.
13. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
14. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedence state.
15. The internal Write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE = V
IL
. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
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