ADC1413D series
Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;
serial JESD204A interface
Rev. 6 — 8 June 2011
Product data sheet
1. General description
The ADC1413D is a dual-channel 14-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performance and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1413D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V source
for analog and a 1.8 V source for the output driver, it embeds two serial outputs. Each lane
is differential and complies with the JESD204A standard. An integrated Serial Peripheral
Interface (SPI) allows the user to easily configure the ADCs. A set of IC configurations is
also available via the binary level control pins taken, which are used at power-up. The
device also includes a programmable full-scale SPI to allow a flexible input voltage range
of 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1413D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
SNR, 72 dBFS; SFDR, 86 dBc
Sample rate up to 125 Msps
Clock input divided by 2 for less jitter
contribution
3 V, 1.8 V power supplies
Flexible input voltage range: 1 V (p-p)
to 2 V (p-p)
Two configurable serial outputs
Compliant with JESD204A serial
transmission standard
Pin compatible with the
ADC1613D series, ADC1213D series,
and ADC1113D125
Input bandwidth, 600 MHz
Power dissipation, 995 mW at 80 Msps
SPI register programming
Duty cycle stabilizer (DCS)
High IF capability
Offset binary, two’s complement, gray
code
Power-down mode and Sleep mode
HVQFN56 package
NXP Semiconductors
ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
3. Applications
Wireless and wired broadband
communications
Spectral analysis
Ultrasound equipment
Portable instrumentation
Imaging systems
Software defined radio
4. Ordering information
Table 1.
Ordering information
Sampling
frequency
(Msps)
125
105
80
65
Package
Name
HVQFN56
HVQFN56
HVQFN56
HVQFN56
Description
Version
Type number
ADC1413D125HN/C1
ADC1413D105HN/C1
ADC1413D080HN/C1
ADC1413D065HN/C1
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8
8
0.85 mm
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8
8
0.85 mm
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8
8
0.85 mm
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8
8
0.85 mm
ADC1413D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 8 June 2011
2 of 43
NXP Semiconductors
ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
5. Block diagram
CFG (0 to 3)
SCLK
SDIO
CS
ERROR
CORRECTION AND
DIGITAL
PROCESSING
SPI
SYNCP
SYNCN
INAP
T/H
INPUT
STAGE
INAM
ADC A CORE
14-BIT
PIPELINED
D13 to D0
OTR
SCRAMBLER A
ENCODER 8-bit/10-bit A
SWING_n
SERIALIZER A
10-bit
OUTPUT
BUFFER A
CMLPA
8-bit
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
FRAME ASSEMBLY
8-bit
CMLNA
CLKP
DLL
PLL
CLKM
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ENCODER 8-bit/10-bit B
SCRAMBLER B
SERIALIZER B
10-bit
OUTPUT
BUFFER B
CMLPB
8-bit
8-bit
INBP
T/H
INPUT
STAGE
INBM
ADC B CORE
14-BIT
PIPELINED
OTR
D13 to D0
CMLNB
SWING_n
CLOCK INPUT
STAGE AND DUTY
CYCLE CONTROL
ADC1413D
SCRAMBLER RESET
REFBT
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
REFAB
REFAT
005aaa067
REFBB
VCMB
VCMA
SENSE VREF
Fig 1.
Block diagram
ADC1413D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 8 June 2011
3 of 43
NXP Semiconductors
ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
6. Pinning information
6.1 Pinning
48 SWING_1
47 SWING_0
44 SYNCN
VDDD 27
INAP
INAM
VCMA
REFAT
REFAB
AGND
CLKP
CLKM
AGND
1
2
3
4
5
6
7
8
9
43 SYNCP
42 DGND
41 DGND
40 VDDD
39 CMLPA
38 CMLNA
37 VDDD
36 DGND
35 DGND
34 VDDD
33 CMLNB
32 CMLPB
31 VDDD
30 DGND
29 DGND
DGND 28
005aaa068
54 SENSE
ADC1413D
REFBB 10
REFBT 11
VCMB 12
INBM 13
INBP 14
VDDA 15
VDDA 16
SCLK 17
SDIO 18
CS 19
AGND 20
RESET 21
SCRAMBLER 22
CFG0 23
CFG1 24
CFG2 25
CFG3 26
Transparent top view
Fig 2.
Pinning diagram
6.2 Pin description
Table 2.
Symbol
INAP
INAM
VCMA
REFAT
REFAB
AGND
CLKP
CLKM
AGND
REFBB
REFBT
VCMB
INBM
ADC1413D_SER
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
Type
[1]
I
I
O
O
O
G
I
I
G
O
O
O
I
Description
channel A analog input
channel A complementary analog input
channel A output common voltage
channel A top reference
channel A bottom reference
analog ground
clock input
complementary clock input
analog ground
channel B bottom reference
channel B top reference
channel B output common voltage
channel B complementary analog input
© NXP B.V. 2011. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 6 — 8 June 2011
45 DGND
52 AGND
51 AGND
46 VDDD
56 VDDA
53 VDDA
50 VDDA
55 VREF
49 DNC
4 of 43
NXP Semiconductors
ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Pin description
…continued
Pin
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Type
[1]
I
P
P
I
I/O
I
G
I
I
I/O
I/O
I/O
I/O
P
G
G
G
P
O
O
P
G
G
P
O
O
P
G
G
I
I
G
P
I
I
O
P
G
G
Description
channel B analog input
analog power supply 3 V
analog power supply 3 V
SPI clock
SPI data input/output
chip select
analog ground
JEDEC digital IP reset
scrambler enable and disable
See
Table 28
(input) or OTRA (output)
[2]
See
Table 28
(input) or OTRB (output)
[2]
See
Table 28
(input)
See
Table 28
(input)
digital power supply 1.8 V
digital ground
digital ground
digital ground
digital power supply 1.8 V
channel B output
channel B complementary output
digital power supply 1.8 V
digital ground
digital ground
digital power supply 1.8 V
channel A complementary output
channel A output
digital power supply 1.8 V
digital ground
digital ground
synchronization from FPGA
synchronization from FPGA
digital ground
digital power supply 1.8 V
JESD204 serial buffer programmable output swing
JESD204 serial buffer programmable output swing
do not connect
analog power supply 3 V
analog ground
analog ground
Table 2.
Symbol
INBP
VDDA
VDDA
SCLK
SDIO
CS
AGND
RESET
SCRAMBLER
CFG0
CFG1
CFG2
CFG3
VDDD
DGND
DGND
DGND
VDDD
CMLPB
CMLNB
VDDD
DGND
DGND
VDDD
CMLNA
CMLPA
VDDD
DGND
DGND
SYNCP
SYNCN
DGND
VDDD
SWING_0
SWING_1
DNC
VDDA
AGND
AGND
ADC1413D_SER
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 8 June 2011
5 of 43
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