ADC1413D_1106 datasheet, PDF - EEWORLD Datasheet

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ADC1413D_1106: DescriptionDual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;serial JESD204A interface; File Size570KB，43 Pages; ManufacturerPhilips Semiconductors (NXP Semiconductors N.V.); Websitehttps://www.nxp.com/

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Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;serial JESD204A interface

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ADC1413D series

Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;

serial JESD204A interface

Rev. 6 — 8 June 2011

Product data sheet

1. General description

The ADC1413D is a dual-channel 14-bit Analog-to-Digital Converter (ADC) optimized for

high dynamic performance and low power at sample rates up to 125 Msps. Pipelined

architecture and output error correction ensure the ADC1413D is accurate enough to

guarantee zero missing codes over the entire operating range. Supplied from a 3 V source

for analog and a 1.8 V source for the output driver, it embeds two serial outputs. Each lane

is differential and complies with the JESD204A standard. An integrated Serial Peripheral

Interface (SPI) allows the user to easily configure the ADCs. A set of IC configurations is

also available via the binary level control pins taken, which are used at power-up. The

device also includes a programmable full-scale SPI to allow a flexible input voltage range

of 1 V to 2 V (peak-to-peak).

Excellent dynamic performance is maintained from the baseband to input frequencies of

170 MHz or more, making the ADC1413D ideal for use in communications, imaging, and

medical applications.

2. Features and benefits



SNR, 72 dBFS; SFDR, 86 dBc



Sample rate up to 125 Msps



Clock input divided by 2 for less jitter

contribution



3 V, 1.8 V power supplies



Flexible input voltage range: 1 V (p-p)

to 2 V (p-p)



Two configurable serial outputs



Compliant with JESD204A serial

transmission standard



Pin compatible with the

ADC1613D series, ADC1213D series,

and ADC1113D125



Input bandwidth, 600 MHz



Power dissipation, 995 mW at 80 Msps



SPI register programming



Duty cycle stabilizer (DCS)



High IF capability



Offset binary, two’s complement, gray

code



Power-down mode and Sleep mode



HVQFN56 package

ADC1413D_1106 Related Products

	ADC1413D_1106	ADC1413D065HN	ADC1413D080HN	ADC1413D105HN	ADC1413D125HN	ADC1413D
Description	Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;serial JESD204A interface	Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;serial JESD204A interface	Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;serial JESD204A interface	Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;serial JESD204A interface	Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;serial JESD204A interface	Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps;serial JESD204A interface

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