PDM31256
3.3V 256K Static RAM
32K x 8-Bit Low Voltage
Features
s
High-speed access times
Com’l: 12, 15, 17 and 20 ns
Ind’l: 15, 17 and 20 ns
s
Low power operation (typical)
- PDM31256SA
Active: 200 mW
Standby: 50 mW
s
Single +3.3V (±0.3V) power supply
s
TTL-compatible inputs and outputs
s
Packages
Plastic SOJ (300 mil) - TSO
Plastic TSOP - T
1
2
3
4
5
6
Description
The PDM31256 is a high-performance CMOS static
RAM organized as 32,768 x 8 bits. This product is
produced in Paradigm’s proprietary CMOS
technology which offers the designer the highest
speed parts. Writing to this device is accomplished
when the write enable (WE) and the chip enable
(CE) inputs are both LOW. Reading is accomplished
when WE remains HIGH and CE and OE are both
LOW.
The PDM31256 operates from a single +3.3V power
supply and all the inputs and outputs are fully TTL-
compatible.
The PDM31256 is available in a 28-pin plastic TSOP
and a 28-pin 300-mil plastic SOJ.
Functional Block Diagram
7
8
9
10
11
12
Rev. 3.0 - 7/24/96
7-1
PDM31256
Pin Configurations
TSOP
SOJ
Pin Description
Name
A14-A0
I/O7-I/O0
OE
WE
CE
V
CC
V
SS
Description
Address Inputs
Data Inputs/Outputs
Output Enable Input
Write Enable Input
Chip Enable Input
Power (+3.3V)
Ground
Truth Table
OE
X
L
X
H
WE
X
H
L
H
CE
H
L
L
L
I/O
Hi-Z
D
OUT
D
IN
Hi-Z
MODE
Standby
Read
Write
Output Disable
NOTE: 1. H = V
IH
, L = V
IL
, X = DON’T CARE
Absolute Maximum Ratings
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
I
OUT
Rating
Terminal Voltage with Respect to Vss
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
Com’l.
–0.5 to +4.6
–55 to +125
–55 to +125
1.0
50
Ind.
–0.5 to +4.6
–65 to +135
–65 to +150
1.0
50
Unit
V
°C
°C
W
mA
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RA
TINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
Symbol
V
CC
V
SS
Commercial
Industrial
Parameter
Supply Voltage
Supply Voltage
Ambient Temperature
Ambient Temperature
Min.
3.0
0
0
–40
Typ.
3.3
0
25
25
Max.
3.6
0
70
85
Unit
V
V
°C
°C
7-2
Rev. 3.0 - 7/24/96
PDM31256
DC Electrical Characteristics
(V
CC
= 3.3V ± 0.3V)
Symbol
I
LI
I
LO
V
IL
V
IH
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 8 mA, V
CC
= Min.
I
OL
= 10 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
Test Conditions
V
CC
= MAX., V
IN
= Vss to V
CC
V
CC
= MAX.,
CE = V
IH
, V
OUT
= Vss to V
CC
Com’l/
Ind.
Com’l/
Ind.
Min.
–5
–5
–0.3
(1)
2.2
—
—
2.4
Max.
5
5
0.8
Vcc+0.3
0.4
0.5
—
Unit
µA
µA
V
V
V
V
1
2
3
4
NOTE:1.V
IL
(min) = –3.0V for pulse width less than 20 ns.
Power Supply Characteristics
-12
Symbol Parameter
I
CC
Operating Current
CE = V
IL
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
OUT
= 0 mA
I
SB
Standby Current
CE = V
IH
f = f
MAX
= 1/t
RC
V
CC
= Max.
I
SB1
Full Standby Current
CE
≥
V
HC
f=0
V
CC
= Max.,
V
IN
≥
V
CC
– 0.2V or
≤
0.2V
10
10
15
10
15
10
15
mA
40
35
35
35
35
30
30
mA
Com’l.
130
-15
-17
-20
Unit
mA
Com’l Ind. Com’l Ind. Com’l Ind.
120
120
120
120
110
110
5
6
7
8
9
NOTES: All values are maximum guaranteed values.
V
LC
≤
0.2V, V
HC
≥
V
CC
– 0.2V
Capacitance
(1)
(T
A
= +25°C, f = 1.0 MHz)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Max.
8
8
Unit
pF
pF
10
11
12
NOTE: 1. This parameter is determined by device characterization but is not production
tested.
Rev. 3.0 - 7/24/96
7-3
PDM31256
AC Test Conditions
Input pulse levels
Input rise and fall times
Input timing reference levels
Output reference levels
Output load
V
SS
to 3.0V
2.5 ns
1.5V
1.5V
See Figures 1 and 2
Figure 1. Output Load Equivalent
Figure 2. Output Load Equivalent
(for t
LZCE
, t
HZCE
, t
LZWE
, t
HZWE
, t
LZOE
,
t
HZOE
)
Figure 3.
7-4
Rev. 3.0 - 7/24/96
PDM31256
Read Cycle No. 1
(1)
1
2
3
Read Cycle No. 2
(2)
4
5
6
7
AC Electrical Characteristics
Description
READ Cycle
READ cycle time
Address access time
Chip enable access time
Output hold from address change
Chip enable to output in low Z
(3,4,5)
Chip disable to output in high Z
(3,4,5)
Chip enable to power up time
(4)
Chip disable to power down time
(4)
Output enable access time
Output enable to output in low Z
(4,5)
Output disable to output in high Z
(4,5)
Sym
t
RC
t
AA
t
ACE
t
OH
t
LZCE
t
HZCE
t
PU
t
PD
t
AOE
t
LZOE
t
HZOE
0
8
0
12
6
0
8
3
5
10
0
15
8
-12
-15
-17
Max
Min
-20
Max
Units
ns
Min. Max. Min. Max. Min
12
12
12
3
5
10
15
15
15
8
9
10
11
12
7-5
17
17
17
3
5
12
0
17
9
0
8
20
20
20
3
5
15
0
20
10
0
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 3.0 - 7/24/96
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