EEWORLDEEWORLDEEWORLD

Part Number

Search

DM74S381N

Description
Arithmetic Logic Unit, S Series, 4-Bit, TTL, PDIP20, PLASTIC, DIP-20
Categorylogic    logic   
File Size106KB,6 Pages
ManufacturerRochester Electronics
Websitehttps://www.rocelec.com/
Download Datasheet Parametric Compare View All

DM74S381N Overview

Arithmetic Logic Unit, S Series, 4-Bit, TTL, PDIP20, PLASTIC, DIP-20

DM74S381N Parametric

Parameter NameAttribute value
MakerRochester Electronics
package instructionDIP,
Reach Compliance Codeunknown
Other featuresCAPABLE OF 3 LOGIC & ARITHMETIC OPERATIONS; INTERNAL CARRY AND HIGHER ORDER LOOKAHEAD
seriesS
JESD-30 codeR-PDIP-T20
length26.075 mm
Logic integrated circuit typeARITHMETIC LOGIC UNIT
Number of digits4
Number of functions1
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Package shapeRECTANGULAR
Package formIN-LINE
propagation delay (tpd)30 ns
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
width7.62 mm

DM74S381N Preview

DM74S381 Arithmetic Logic Unit Function Generator
June 1989
DM74S381 Arithmetic Logic
Unit Function Generator
General Description
The ’S381 is a Schottky TTL arithmetic logic unit (ALU)
function generator that performs eight binary arithmetic log-
ic operations on two 4-bit words as shown in the function
table These operations are selected by the three function-
select lines (S0 S1 S2) A full carry look-ahead circuit is
provided for fast simultaneous carry generation by means
of two cascade outputs (P and G) for the four bits in the
package The method of cascading 54S182 74S182 look-
ahead carry generators with these ALU’s to provide multi-
level full carry look-ahead is illustated under typical applica-
tions data for the ’S182 The typical addition times shown
illustrate the short delay time required for addition of longer
words when full look-ahead is employed The exclusive-OR
AND or OR function of two Boolean variables is provided
without the use of external circuitry Also the outputs can
be either cleared (low) or preset (high) as desired
Features
Y
Y
Y
Y
Y
A fully parallel 4-Bit ALU in 20-pin package for 0 300-
inch row spacing
Ideally suited for high-density economical processors
Parallel inputs and outputs and full look-ahead provide
system flexibility
Arithmetic and logic operations selected specifically to
simplify system implementation
A minus B
B minus A
A plus B
and five other functions
Schottky-clamped for high performance
16-bit add time
26 ns typ using look-ahead
32-bit add time
34 ns typ using look-ahead
Connection Diagram
Dual-In-Line Package
Pin Designations
Designation
A3 A2 A1 A0
B3 B2 B1 B0
S2 S1 S0
Pin Nos
17 19 1 3
16 18 2 4
7 6 5
Function
Word A Inputs
Word B Inputs
Function-Select
Inputs
Carry Input for
Addition Inverted
Carry Input for
Subtraction
Function Outputs
Inverted Carry
Propagate Output
Inverted Carry
Generated Output
Supply Voltage
Ground
C
n
F3 F2 F1 F0
TL F 6487 – 1
15
12 11 9 8
14
13
20
10
Order Number DM74S381N
See NS Package Number N20A
P
G
Function Table
Selection
S2
L
L
L
L
H
H
H
H
S1
L
L
H
H
L
L
H
H
S0
L
H
L
H
L
H
L
H
Arithmetic Logic
Operation
CLEAR
B MINUS A
A MINUS B
A PLUS B
A
Z
B
A
a
B
AB
PRESET
V
CC
GND
H
e
high level L
e
low level
C
1995 National Semiconductor Corporation
TL F 6487
RRD-B30M105 Printed in U S A
Absolute Maximum Ratings
(Note)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
5 5V
0 C to
a
70 C
b
65 C to
a
150 C
Note
The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed The device should not be operated at these limits The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Parameter
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
0
Min
4 75
2
08
b
1
Nom
5
Max
5 25
Units
V
V
V
mA
mA
C
20
70
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
I
I
I
IH
Parameter
Input Clamp Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Current
Input Voltage
Max
Conditions
V
CC
e
Min I
I
e b
18 mA
V
CC
e
Min I
OH
e
Max
V
IL
e
Max V
IH
e
Min
V
CC
e
Min I
OL
e
Max
V
IH
e
Min V
IL
e
Max
V
CC
e
Max V
I
e
5 5V
V
CC
e
Max
V
I
e
2 7V
Any S
Cn
Any Other
I
IL
Low Level Input
Current
V
CC
e
Max
V
I
e
0 5V
Any S
Cn
Any Other
I
OS
I
CC
Short Circuit
Output Current
Supply Current
V
CC
e
Max (Note 2)
V
CC
e
Max
b
40
Min
Typ
(Note 1)
Max
b
1 2
Units
V
V
27
34
05
1
50
250
200
b
2
b
8
b
6
b
100
V
mA
High Level Input
Current
mA
mA
mA
mA
105
160
Note 1
All typicals are at V
CC
e
5V T
A
e
25 C
Note 2
Not more than one output should be shorted at a time and the duration should not exceed one second
2
Switching Characteristics
at V
CC
e
5V and T
A
e
25 C (See Section 1 for Test Waveforms and Output Load)
R
L
e
280X
Symbol
Parameter
From (Input)
To (Output)
Cn to
Any F
Cn to
Any F
A or B
to G
A or B
to G
A or B
to P
A or B
to P
A
i
or B
i
to F
i
A
i
or B
i
to F
i
S to
Any
S to
Any
C
L
e
15 pF
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Max
17
17
20
20
18
18
27
25
30
30
C
L
e
50 pF
Min
Max
19
19
23
23
21
21
30
27
33
33
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
3
Logic Diagram
TL F 6487 – 2
4
5

DM74S381N Related Products

DM74S381N
Description Arithmetic Logic Unit, S Series, 4-Bit, TTL, PDIP20, PLASTIC, DIP-20
Maker Rochester Electronics
package instruction DIP,
Reach Compliance Code unknown
Other features CAPABLE OF 3 LOGIC & ARITHMETIC OPERATIONS; INTERNAL CARRY AND HIGHER ORDER LOOKAHEAD
series S
JESD-30 code R-PDIP-T20
length 26.075 mm
Logic integrated circuit type ARITHMETIC LOGIC UNIT
Number of digits 4
Number of functions 1
Number of terminals 20
Maximum operating temperature 70 °C
Package body material PLASTIC/EPOXY
encapsulated code DIP
Package shape RECTANGULAR
Package form IN-LINE
propagation delay (tpd) 30 ns
Maximum seat height 5.08 mm
Maximum supply voltage (Vsup) 5.25 V
Minimum supply voltage (Vsup) 4.75 V
Nominal supply voltage (Vsup) 5 V
surface mount NO
technology TTL
Temperature level COMMERCIAL
Terminal form THROUGH-HOLE
Terminal pitch 2.54 mm
Terminal location DUAL
width 7.62 mm
WinCE5.0 system failed to start, please give me some advice
The following is the prompt of DNW output: Microsoft Windows CE Ethernet Bootloader Common Library Version 1.0 Built Mar 13 2003 23:05:42 FMD::FMD_Init FMD::FMD_Init Done TOC_Read -TOC_Read YCTek 2440...
dwday Embedded System
Do not connect copper wire and aluminum wire together
[align=left][size=4]Briefly introduce the advantages and disadvantages of copper wire and aluminum wire: [/size][/align][align=left][size=4]For the same area [/size][/align][align=left][size=4] [/size...
qwqwqw2088 Analogue and Mixed Signal
How to understand the following codes
#define Set_Cs GPIOD-ODR |= ( 112 );#define Clr_Cs GPIOD-ODR = ~( 112 ); #define Set_Rs GPIOD-ODR |= ( 113 );#define Clr_Rs GPIOD-ODR = ~( 113 ); #define Set_nWr GPIOD-ODR |= ( 114 );#define Clr_nWr G...
yangzichen stm32/stm8
Is there a problem with the FPGA minimum system?
Dear experts, this is the FPGA minimum system I drew by myself. After soldering, I can download the program, but the program does not seem to run. All pins output high level. I don’t know if there is ...
沉默珏殇 FPGA/CPLD
BlueNRG/-MS default firmware configuration? ?
BlueNRG-MS has its own BLE stack firmware. Its peripheral connections vary depending on the firmware configuration, such as 16MHZ/32MHZ? SMPS ON/OFF, 32K internal/external? So I want to know what the ...
melau MEMS sensors
Advantages and prospects of CC1312R compared with CC1310
1. Introduction to CC1310 CC1310 is a cost-effective ultra-low power RF device below 1GHz. It is highly integrated with active RF and MCU with ultra-low current consumption. This excellent performance...
火辣西米秀 Wireless Connectivity

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1655  255  502  1717  2817  34  6  11  35  57 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号