X68C64
68XX Microcontroller Family Compatible
64K
X68C64
E
2
Micro-Peripheral
DESCRIPTION
8192 x 8 Bit
FEATURES
•
•
•
•
•
•
•
•
CONCURRENT READ WRITE
™
—Dual Plane Architecture
—Isolates Read/Write Functions
Between Planes
—Allows Continuous Execution of Code
From One Plane While Writing in
the Other Plane
Multiplexed Address/Data Bus
—Direct Interface to Popular 8-bit
Microcontrollers, e.g., Motorola M6801/03,
M68HC11 Family
High Performance CMOS
—Fast Access Time, 120ns
—Low Power
—60mA Maximum Active
—500
µ
A Maximum Standby
Software Data Protection
Block Protect Register
—Individually Set Write Lock Out in 1K Blocks
Toggle Bit Polling
—Early End of Write Detection
Page Mode Write
—Allows up to 32 Bytes to be Written in
One Write Cycle
High Reliability
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
The X68C64 is an 8K x 8 E
2
PROM fabricated with
advanced CMOS Textured Poly Floating Gate Technol-
ogy. The X68C64 features a Multiplexed Address and
Data bus allowing a direct interface to a variety of
popular single-chip microcontrollers operating in ex-
panded multiplexed mode without the need for addi-
tional interface circuitry.
The X68C64 is internally configured as two independent
4K x 8 memory arrays. This feature provides the ability
to perform nonvolatile memory updates in one array and
continue operation out of code stored in the other array;
effectively eliminating the need for an auxiliary memory
device for code storage.
To write to the X68C64, a three-byte command
sequence must precede the byte(s) being written. The
X68C64 also provides a second generation software
data protection scheme called Block Protect. Block
Protect can provide write lockout of the entire device or
selected 1K blocks. There are eight 1K x 8 blocks that
can be write protected individually in any combination
required by the user. Block Protect, in addition to Write
Control input, allows the different segments of the memory
to have varying degrees of alterability in normal system
operation.
FUNCTIONAL DIAGRAM
WC
CE
R/W
E
SEL
A8–A11
CONTROL
LOGIC
X
D
E
C
O
D
E
SOFTWARE
DATA
PROTECT
A12
1K BYTES
1K BYTES
1K BYTES
1K BYTES
A12
M
U
X
1K BYTES
1K BYTES
1K BYTES
1K BYTES
A12
AS
L
A
T
C
H
E
S
Y DECODE
I/O & ADDRESS LATCHES AND BUFFERS
A/D0–A/D7
3868 FHD F02
CONCURRENT READ WRITE
™
is a trademark of Xicor, Inc.
© Xicor, Inc. 1998 Patents Pending
3868-2.7 5/6/98 T0/C0/D1 SH
1
Characteristics subject to change without notice
X68C64
PIN DESCRIPTIONS
Address/Data (A/D
0
–A/D
7
)
Multiplexed low-order addresses and data. The ad-
dresses flow into the device while AS is HIGH. After AS
transitions from a HIGH to LOW the addresses are
latched. Once the addresses are latched these pins
input data or output data depending on E, R/W, and CE.
Addresses (A
8
–A
12
)
High order addresses flow into the device when AS is
HIGH and are latched when AS goes LOW.
Chip Enable (CE)
The Chip Enable input must be HIGH to enable all read/
write operations. When CE is LOW and AS is LOW, the
X68C64 is placed in the low power standby mode.
Enable (E)
When used with a MC6801 or MC6803, the E input is tied
directly to the E output of the microcontroller.
Read/Write (R/W)
When used with a MC6801 or MC6803, the R/W input is
tied directly to the R/W output of the microcontroller.
Address Strobe (AS)
Addresses flow through the latches to address decoders
when AS is HIGH and are latched when AS transitions
from a HIGH to LOW.
Device Select (SEL)
Must be connected to V
SS
.
Write Control (WC)
The Write Control allows external circuitry to abort a
page load cycle once it has been initiated. This input is
useful in applications in which a power failure or proces-
sor RESET could interrupt a page load cycle. In this
case, the microcontroller might drive all signals HIGH,
causing bad data to be latched into the E
2
PROM. If the
Write Control input is driven HIGH (before t
TBLC
Max)
after Read/Write (R/W) goes HIGH, the write cycle will
be aborted.
When
WC
is LOW (tied to V
SS
) the X68C64 will be
enabled to perform write operations. When
WC
is HIGH
normal read operations may be performed, but all at-
tempts to write to the device will be disabled.
PIN NAMES
Symbol
AS
A/D
0
–A/D
7
A
8
–A
12
E
R/W
CE
WC
SEL
V
SS
V
CC
NC
Description
Address Strobe
Address Inputs/Data I/O
Address Inputs
Enable Input
Read/Write Input
Chip Enable
Write Control
Device Select—Connect to V
SS
Ground
Supply Voltage
No Connect
3868 PGM T01.1
PIN CONFIGURATION
DIP/SOIC
NC
A12
NC
NC
WC
SEL
A/D0
A/D1
A/D2
A/D3
A/D4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
X68C64
24
23
22
21
20
19
18
17
16
15
14
13
VCC
R/W
AS
A8
A9
A11
E
A10
CE
A/D7
A/D6
A/D5
3868 FHD F01.1
2
X68C64
PRINCIPLES OF OPERATION
The X68C64 is a highly integrated peripheral device for
a wide variety of single-chip microcontrollers. The
X68C64 provides 8K bytes of E
2
PROM which can be
used either for Program Storage, Data Storage, or a
combination of both in systems based upon Von
Neumann (68XX) architectures. The X68C64 incorpo-
rates the interface circuitry normally needed to decode
the control signals and demultiplex the Address/Data
bus to provide a “Seamless” interface.
The interface inputs on the X68C64 are configured such
that it is possible to directly connect them to the proper
interface signals of the appropriate single-chip
microcontroller.
The X68C64 is internally organized as two independent
planes of 4K bytes of memory with the A
12
input select-
ing which of the two planes of memory are to be
accessed. While the processor is executing code out of
one plane, write operations can take place in the other
plane, allowing the processor to continue execution of
code out of the X68C64 during a byte or page write to the
device.
The X68C64 also features an advanced implementation
of the Software Data Protection scheme, called Block
Protect, which allows the device to be broken into 8
independent sections of 1K bytes. Each of these sec-
tions can be independently enabled for write operations;
thereby allowing certain sections of the device to be
secured so that updates can only occur in a controlled
environment (e.g. in an automotive application, only at
an authorized service center). The desired set-up con-
figuration is stored in a nonvolatile register, ensuring the
configuration data will be maintained after the device is
powered down.
The X68C64 also features a Write Control input (WC),
which serves as an external control over the completion
of a previously initiated page load cycle.
The X68C64 also features the industry standard
E
2
PROM characteristics such a byte or page mode
write and Toggle Bit Polling.
DEVICE OPERATION
Motorola 68XX operation requires the microcontroller’s
AS, E, and R/W outputs tied to the X68C64 AS, E, and
R/W inputs respectively.
The falling edge of AS will latch the addresses for both
a read and write operation. The state of R/W output
determines the operation to be performed, with the E
signal acting as a data strobe.
If R/W is HIGH and CE HIGH (read operation), data will
be output on A/D
0
–A/D
7
after E transitions HIGH. If
R/W is LOW and CE is HIGH (write operation), data
presented at A/D
0
–A/D
7
will be strobed into the X68C64
on the HIGH to LOW transition of E.
Typical Application
30
XTAL
8 MHz
OSC.
29
8
EXTAL
V
CC
V
CC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PB0
PB1
PB2
PB3
PB4
PB7
31
32
33
34
35
36
37
38
16
15
14
13
12
9
25
24
MODA
MODB
26
AS
27
E
28
R/W
7
8
9
10
11
13
14
15
21
20
17
19
2
16
5
22
18
23
6
24
A/D0 V
CC
A/D1
A/D2
A/D3
A/D4
A/D5
A/D6
A/D7
A8
A9
A10
A11
A12
CE
WC
AS
E
R/W
SEL
V
SS
X68C64
12
68HC11A8
3868 ILL F03.2
3
X68C64
MODE SELECTION
CE
V
SS
LOW
HIGH
HIGH
E
X
X
HIGH
R/W
X
X
HIGH
LOW
Mode
Standby
Standby
Read
Write
I/O
High Z
High Z
D
OUT
D
IN
Power
Standby (CMOS)
Standby (TTL)
Active
Active
3868 PGM T02.1
PAGE WRITE OPERATION
Regardless of the microcontroller employed, the X68C64
supports page mode write operations. This allows the
microcontroller to write from one to thirty-two bytes of
data to the X68C64. Each individual write within a page
write operation must conform to the byte write timing
requirements. The rising edge of E starts a timer delay-
ing the internal programming cycle 100µs. Therefore,
each successive write operation must begin within 100µs
of the last byte written. The following waveforms illus-
trate the sequence and timing requirements.
Page Write Timing Sequence for E Controlled Operation
OPERATION
BYTE 0
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
CE
AS
A/D0–A/D7
AIN
DIN
AIN
DIN
AIN
DIN
AIN
DIN
AIN
DIN
AIN
AIN
A8–A12
A12=n
A12=n
A12=n
A12=n
A12=x
ADDR
Next Address
E
R/W
tBLC
tWC
3868 FHD F07
Notes:
(1) For each successive write within a page write cycle A
5
–A
12
must be the same.
(2) Although it is not illustrated, the microcontroller may interleave read operations between the individual byte writes within the page
write operation. Two responses are possible.
a. Reading from the same plane being written (A
12
of Read = A
12
of Write) is effectively a Toggle Bit Polling operation.
b. Reading from the opposite plane being written (A
12
of Read
≠
A
12
of Write) true data will be returned, facilitating the use of a
single memory component as both program and data storage.
4
X68C64
Toggle Bit Polling
Because the X68C64 typical nonvolatile write cycle time
is less than the specified 5ms, Toggle Bit Polling has
been provided to determine the early completion of
write. During the internal programming cycle, I/O
6
will
toggle from HIGH to LOW and LOW to HIGH on subse-
quent attempts to read the device. When the internal
Toggle Bit Polling E Control
OPERATION
LAST BYTE
WRITTEN
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X68C64 READY FOR
NEXT OPERATION
cycle is complete, the toggling will cease and the device
will be accessible for additional read or write operations.
Due to the dual plane architecture, reads for polling must
occur in the plane that is being written; that is, the state
of A
12
during a write must match the state of A
12
during
Toggle Bit Polling.
*
CE
AS
A/D0–A/D7
AIN
DIN
AIN
DOUT
AIN
DOUT
AIN
DOUT
AIN
DOUT
AIN
A8–A12
A12=n
A12=n
A12=n
A12=n
A12=n
ADDR
E
R/W
3868 FHD F08
*Minimum time delay of 200µs is required between the last bye write and start of the toggle bit polling sequence.
SYMBOL TABLE
WAVEFORM
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
5
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