X68C75JSLIC datasheet, PDF - EEWORLD Datasheet

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X68C75JSLIC: DescriptionParallel I/O Port, 16 I/O, CMOS, PQCC44, PLASTIC, LCC-44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size305KB，26 Pages; ManufacturerXicor Inc.

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X68C75JSLIC Overview

Parallel I/O Port, 16 I/O, CMOS, PQCC44, PLASTIC, LCC-44

X68C75JSLIC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Xicor Inc.
package instruction	PLASTIC, LCC-44
Reach Compliance Code	unknown
External data bus width	8
JESD-30 code	S-PQCC-J44
JESD-609 code	e0
length	16.5862 mm
Number of I/O lines	16
Number of ports	2
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC44,.7SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum slew rate	60 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	16.5862 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE

X68C75JSLIC Preview

PPLICATION

OTES

A V A I L A B L E

AN62 • AN64

X68C75 SLIC

•

AN66 • AN74

SLIC

X68C75 SLIC

Microperipheral

Port Expander and

Memory

• High Performance CMOS

—Fast Access Time, 120ns

—Low Power

• 60mA Active

• 100

A Standby

• PDIP, PLCC, and TQFP Packaging Available

DESCRIPTION

The X68C75 is a highly integrated peripheral for the

68HC11 family of microcontrollers. The device inte-

grates 8K-bytes of 5V byte-alterable nonvolatile memory,

2 bidirectional 8-bit ports, 16 general purpose registers,

programmable internal address decoding and a multi-

plexed address and data bus.

The 5V byte-alterable nonvolatile memory can be used

as program storage, data storage, or a combination of

both. The memory array is separated into two 4K-byte

sections which allows read accesses to one section

while a write operation is taking place in the other

section. The nonvolatile memory also features Software

Data Protection to protect the contents during power

transitions, and an advanced Block Protect register

which allows individual blocks of the memory to be

configured as read-only or read/write.

FEATURES

• Highly Integrated Microcontroller Peripheral

—8K x 8 E

Memory

—2 x 8 General Purpose Bidirectional I/O Ports

—16 x 8 General Purpose Registers

—Integerated Interrupt Controller Module

—Internal Programmable Address Decoding

• Self Loading Integrated Code (SLIC)

—On-Chip BIOS and Boot Loader

—IBM/PC Based Interface Software(XSLIC)

• Concurrent Read During Write

—Dual Plane Architecture

• Isolates Read/Write Functions Between

Planes

• Allows Continuous Execution Of Code

From One Plane While Writing In The

Other Plane

• Multiplexed Address/Data Bus

—Direct Interface to Popular 68HC11 Family of

Microcontrollers

• Software Data Protection

—Protect Entire Array During Power-up/-down

• Block Lock™ Data Protection

—Set Write Lockout in 1K Blocks

• Toggle Bit Polling

PIN CONFIGURATIONS

DIP

RESET

A12

SEL

STRA

A15

A14

A13

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

A/D0

A/D1

A/D2

A/D3

A/D4

VSS

X68C75

VCC

R/W

PLCC

TQFP

STRA

RESET

VCC

SEL

A15

A12

A11

IRQ

STRB

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

A10

A/D7

A/D6

A/D5

2899 ILL F01

INDEX

CORNER

A14

A13

PA7

PA6

PA5

PA4

PA3

1 44 43 42 41 40

A11

IRQ

STRB

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

R/W

X68C75

SLIC

PA2

PA1

PA0

A/D0

18 19 20 21 22 23 24 25 26 27 28

A/D1

A/D2

A/D3

A/D4

VSS

A/D5

A/D6

A/D7

A10

2899 ILL F02.3

Concurrent Read During Write, Block Lock, and SLIC

are registered trademarks of Xicor, Inc.

©Xicor, Inc. 1994, 1995, 1996 Patents Pending

2899-2.1 4/11/97 T0/C0/D1 SH

Characteristics subject to change without notice

X68C75 SLIC

Each bidirectional port consists of 8 general purpose

I/O lines and 1 data strobe line. The ports also feature a

configurable interrupt request output.

Access to the X68C75 is accomplished through the

multiplexed address/data bus of the 68HC11 type con-

trollers. An internal programmable address decoder

maps the internal memory and register locations into the

desired address space.

ARCHITECTURAL OVERVIEW

The X68C75 incorporates the interface circuitry nor-

mally needed to decode the control signals and

demultiplex the address/data bus to provide a “seam-

less” interface.

The control inputs on the X68C75 are configured such

that it is possible to directly connect them to the proper

interface signals of the 68HC11 microcontroller. The

reading of data from the chip is controlled by the

R/W and E clock signals.

Reading and writing of the nonvolatile memory array is

analogous to RAM operation. During a write operation to

either the nonvolatile memory or the control registers,

the falling edge of AS latches the address present on the

FUNCTIONAL DIAGRAM

address bus into the X68C75, and the falling edge of E

clock latches the data to be written.

The nonvolatile memory of the X68C75 is internally

organized as two independent arrays of 4K-bytes with

the A12 input selecting which of the two planes of

memory is to be accessed. While the processor is

executing code out of one plane, write operations can

take place in the other plane; allowing the processor to

continue execution of code out of the X68C75 during a

byte or page write to the device. This feature is called

Concurrent Read During Write.

The X68C75 also features an advanced implementation

of the Software Data Protection scheme, called Block

Protect, which allows the nonvolatile memory array to be

treated as 8 independent sections of 1K-bytes. Each of

these sections can be independently enabled for write

operations. This allows segmentation of the memory

contents into writable and non-writable sections, thereby,

allowing certain sections of the device to be secured so

that updates can only occur in a controlled environ-

ment. (e.g. in an automotive application, only at an

authorized service center). The Block Protect configu-

ration is stored in a nonvolatile register, ensuring that

the configuration data will be maintained after the

device is powered-down.

ADDRESS

A0–A15

LATCH

LEFT PLANE

DECODE

RIGHT PLANE

DECODE

16 X 8

GENERAL

PURPOSE

REGISTERS

1K X 8

I/O

BUFFER

LATCH

1K X 8

E2PROM

1K X 8

E2PROM

1K X 8

PORT

I/O0–I/O7

R/W

SEL

RESET

IRQ

SDP

DECODE

PORT

DATA I/O BUS

MASTER

CONTROL

LOGIC

PORT SELECT

MEM.

MAP

CONFIG

PORT

SPECIAL

FUNCTION

REGISTERS

2899 ILL F03

X68C75 SLIC

The X68C75 write control input, serves as an external

control over the completion of a previously initiated page

load cycle.

The X68C75 also features the industry standard 5V E

memory characteristics such as byte or page mode write

and Toggle Bit Polling.

Read

A HIGH to LOW transition on AS latches the address;

the data will be output on the AD pins when E clock and

R/W are HIGH (t

ACC

Write

A write is performed by latching the address on the

falling edge of AS. The R/W signal LOW while E clock is

HIGH initiates a write cycle. The valid data must be

present on AD

-AD

prior to an E clock HIGH to LOW

PIN DESCRIPTIONS

PIN NAME

–A

–AD

I/O

DESCRIPTION

Non-multiplexed high-order Address line inputs for the upper byte of the address. The addresses are

latched when AS makes a HIGH to LOW transition.

Multiplexed lower-order Address and DATA lines. The addresses are latched when AS makes a

HIGH to LOW transition.

Address Strobe input is used to latch the addresses present on the address lines A

–A

and AD

–

into the device. The addresses are latched when AS transitions from HIGH to LOW.

The device select (CE) is an active HIGH input. This signal has to be asserted prior to AS HIGH to

LOW transition in order to generate a valid internal device select signal. Holding this pin LOW and

AS LOW will place the device in standby mode. The ports stay active at all times.

The E clock is the bus frequency clock input, and is used as a data timing reference signal. When

the E clock is LOW, the addresses are latched by HIGH to LOW transition on the AS pin. The E

clock HIGH cycle is used for data transfers.

The

IRQ

is an open-drain output. It can be configured to signal latching of new data into the ports,

and completion of

an E

memory write cycle.

The I/O lines of port A. The output driver can be configured as either CMOS or open-drain using the

AWO bit in CR. The I/O direction bit (DIRA) in CR is used to select the port A I/O mode.

The I/O lines of port B. The output driver can be configured as either CMOS or open-drain using the

BWO bit in CR. The I/O direction bit (DIRB) in CR is used to select the port B I/O mode.

The R/W signal indicates the direction of data transfers. During phase 2 (HIGH cycle) of the E clock,

the R/W is HIGH for a read, and LOW for a write cycle.

RESET

is used to initialize the internal static registers and has no effect on the E

memory opera-

tions. The default active level is LOW, but it can be reconfigured in EEM register.

The

SEL

input should be LOW for the device to be selected. This input is normaly tied to V

The STRA controls port A and STRB controls port B. When ports are configured as inputs, a valid

transition on their strobe pins will latch into their Port Data Register the data present at the port input

pins. Writing to an output port Data Register generates a pulse of fixed duration on its corresponding

strobe pin. The output data presented at the output pins stay valid until the next data is written to the

output port data register.

input has to be held LOW during a write cycle. It can be permanently tied HIGH in order to

disable writes to the E

memory. Taking the

HIGH prior to t

BLC

(100µs; the time delay from the

last write cycle to the start of internal programming cycle) will inhibit the write operation.

2899 PGM T01.1

transition. The data will be latched into the X68C75 on

the falling edge of E clock.

Page Write Operation

The X68C75 supports page mode write operations. This

allows the microcontroller to write from one to thirty-two

bytes of data to the X68C75. Each individual write within

a page write operation must conform to the byte write

timing requirements. The rising edge of E clock starts a

timer delaying the internal programming cycle 100µs,

therefore, each successive write operation must begin

within 100µs of the last byte written. The waveform

on page 19 illustrates the sequence and timing

requirements.

Toggle Bit Polling

Because the X68C75 typical write timing is less than the

specified 5ms, Toggle Bit Polling has been provided to

IRQ

–PA

–PB

R/W

RESET

SEL

STRA, STRB

I/O

X68C75 SLIC

determine the early completion of a write cycle. During

the internal programming cycle, I/O

will toggle from “1”

to “0” and “0” to “1” on subsequent attempts to read from

the memory plane that is being updated. When the

internal cycle is complete, the toggling will cease and the

device will be accessible for additional read or write

operations. Due to the dual plane architecture, reads for

polling must occur from the plane that was written; that

is, the state of A

during a write must match the state of

during polling.

Figure 1. Toggle Bit Polling E Control

OPERATION

LAST BYTE

WRITTEN

I/O6=X

X68C75 READY FOR

NEXT OPERATION

DATA PROTECTION

The X68C75 provides two levels of data protection

through software control. There is a global software data

protection feature similar to the industry standard for

PROMs and a new Block Lock Protect write lockout

protection providing a secondary level data security

option.

A/D0–A/D7

AIN

DIN

AIN

DOUT

AIN

DOUT

AIN

DOUT

AIN

DOUT

AIN

A8–A12

A12=n

ADDR

R/W

2899 ILL F05

X68C75 SLIC

Software Data Protection

Software Data Protection (SDP) can be employed to

protect the entire array against inadvertent writes during

power-up/power-down operations. The X68C75 is

shipped from the factory with SDP enabled. With SDP

enabled, inadvertent attempts to write to the X68C75 will

be blocked.

The system can still write data, but only when the write

operation (page or byte) is preceded by the three-byte

command sequence. All write operations, both the com-

mand sequence and any data write operations must

conform to the page write timing requirements.

The SDP mode is also enabled anytime one of the

nonvolatile configuration registers are modified. These

include writing to EE map, SFR map, and BPR.

Block Lock Protect Write Lockout

The X68C75 provides a second level of data security

referred to as Block Lock Protect write lockout (or Block

Protection). This is accessed through an extension of

the SDP command sequence. Block Protect allows the

user to lockout writes to 1K x 8 blocks of memory. Unlike

SDP which prevents inadvertent writes, but still allows

Figure 2. Writing with SDP Enabled

b2 b1 b0 P 555

easy system access to writing the memory, Block Pro-

tect will lockout all attempts unless it is specifically

disabled by issuing the deactivation sequence. This

feature can be used to set a higher level of protection in

a system where a portion of the memory is used to store

the system kernel and protect it from the application

programs residing in the other blocks.

Setting write lockout is accomplished by writing a five-

byte command sequence opening access to the Block

Protect Register (BPR). After the fifth byte is written, the

user writes to the BPR, selecting which blocks to protect

or unprotect. All write operations, both the command

sequence and writing the data to the BPR, must conform

to the page write timing requirements. It should be noted

that accessing the BPR automatically sets the upper

level SDP. If for some reason the user does not want

SDP enabled, they may reset it using the normal reset

command sequence. This will

not

affect the state of the

BPR and any 1K x 8 blocks that were set to the write

lockout state will remain in the write lockout state.

Figure 3. Sequence to Deactivate

Software Data Protection

b2 b1 b0 P 555

b2 b1 b0 P AAA

b2 b1 b0 P 555

Perform Byte or Page

Write Operations

b2 b1 b0 P AAA

Delay of t

Exit Routine

2899 ILL F05B

Exit Routine

2899 ILL F05C

b2 b1 b0 Reference the A15–A13

setting in EEM register

P = Address bit (A12) of the

updated memory plane.

b2 b1 b0 Reference the A15–A13

setting in EEM register

P = Address bit (A12) of the

memory plane not being read.

More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

X68C75JSLIC Related Products

	X68C75JSLIC	X68C75LSLIC	X68C75LISLIC	X68C75JMSLIC	X68C75JISLIC	X68C75PISLIC	X68C75PMSLIC	X68C75PSLIC
Description	Parallel I/O Port, 16 I/O, CMOS, PQCC44, PLASTIC, LCC-44	Parallel I/O Port, 16 I/O, CMOS, PQFP44, TQFP-44	Parallel I/O Port, 16 I/O, CMOS, PQFP44, TQFP-44	Parallel I/O Port, 16 I/O, CMOS, PQCC44, PLASTIC, LCC-44	Parallel I/O Port, 16 I/O, CMOS, PQCC44, PLASTIC, LCC-44	Parallel I/O Port, 16 I/O, CMOS, PDIP48, PLASTIC, DIP-48	Parallel I/O Port, 16 I/O, CMOS, PDIP48, PLASTIC, DIP-48	Parallel I/O Port, 16 I/O, CMOS, PDIP48, PLASTIC, DIP-48
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.	Xicor Inc.
package instruction	PLASTIC, LCC-44	TQFP-44	TQFP-44	PLASTIC, LCC-44	PLASTIC, LCC-44	PLASTIC, DIP-48	PLASTIC, DIP-48	PLASTIC, DIP-48
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
External data bus width	8	8	8	8	8	8	8	8
JESD-30 code	S-PQCC-J44	S-PQFP-G44	S-PQFP-G44	S-PQCC-J44	S-PQCC-J44	R-PDIP-T48	R-PDIP-T48	R-PDIP-T48
JESD-609 code	e0	e0	e0	e0	e0	e0	e0	e0
length	16.5862 mm	10 mm	10 mm	16.5862 mm	16.5862 mm	61.785 mm	61.785 mm	61.785 mm
Number of I/O lines	16	16	16	16	16	16	16	16
Number of ports	2	2	2	2	2	2	2	2
Number of terminals	44	44	44	44	44	48	48	48
Maximum operating temperature	70 °C	70 °C	85 °C	125 °C	85 °C	85 °C	125 °C	70 °C
Minimum operating temperature	-	-	-40 °C	-55 °C	-40 °C	-40 °C	-55 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	LQFP	LQFP	QCCJ	QCCJ	DIP	DIP	DIP
Encapsulate equivalent code	LDCC44,.7SQ	TQFP44,.47SQ,32	TQFP44,.47SQ,32	LDCC44,.7SQ	LDCC44,.7SQ	DIP48,.6	DIP48,.6	DIP48,.6
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	CHIP CARRIER	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	CHIP CARRIER	CHIP CARRIER	IN-LINE	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	1.6 mm	1.6 mm	4.57 mm	4.57 mm	5.71 mm	5.71 mm	5.71 mm
Maximum slew rate	60 mA	60 mA	60 mA	60 mA	60 mA	60 mA	60 mA	60 mA
Maximum supply voltage	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V	5.5 V
Minimum supply voltage	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V	4.5 V
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	YES	YES	YES	YES	YES	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	MILITARY	INDUSTRIAL	INDUSTRIAL	MILITARY	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	J BEND	GULL WING	GULL WING	J BEND	J BEND	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	1.27 mm	0.8 mm	0.8 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	2.54 mm
Terminal location	QUAD	QUAD	QUAD	QUAD	QUAD	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
width	16.5862 mm	10 mm	10 mm	16.5862 mm	16.5862 mm	15.24 mm	15.24 mm	15.24 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE

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