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DISCRETE SEMICONDUCTORS
DATA SHEET
age
M3D087
BSP130
N-channel enhancement mode
vertical D-MOS transistor
Product specification
Supersedes data of 1997 Jun 23
2001 Dec 11
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
FEATURES
•
Direct interface to C-MOS, TTL, etc.
•
High-speed switching
•
No secondary breakdown.
APPLICATIONS
•
Line current interruptor in telephone sets
•
Relay, high-speed and line transformer drivers.
handbook, halfpage
BSP130
PINNING - SOT223
PIN
1
2
3
4
gate
drain
source
drain
DESCRIPTION
4
d
DESCRIPTION
N-channel enhancement mode vertical D-MOS transistor
in a SOT223 package.
1
Top view
Marking code
BSP130.
2
3
MAM054
g
s
Fig.1 Simplified outline and symbol.
QUICK REFERENCE DATA
SYMBOL
V
DS
I
D
P
tot
V
GSO
R
DSon
V
GSoff
PARAMETER
drain-source voltage (DC)
drain current (DC)
total power dissipation
gate-source voltage
drain-source on-state
resistance
gate-source cut-off voltage
T
amb
≤
25
°C
open drain
I
D
= 250 mA; V
GS
= 10 V
I
D
= 1 mA; V
DS
= V
GS
CONDITIONS
−
−
−
−
−
0.8
MIN.
MAX.
300
350
1.5
±20
6
2
V
mA
W
V
Ω
V
UNIT
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
V
DS
V
GSO
I
D
I
DM
P
tot
T
stg
T
j
Note
1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm
2
.
PARAMETER
drain-source voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
T
amb
≤
25
°C;
note 1
open drain
CONDITIONS
−
−
−
−
−
−55
−
MIN.
MAX.
300
±20
350
1.4
1.5
+150
150
V
V
mA
A
W
°C
°C
UNIT
2001 Dec 11
2
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
THERMAL CHARACTERISTICS
SYMBOL
R
th j-a
Note
PARAMETER
thermal resistance from junction to ambient; note 1
VALUE
83.3
BSP130
UNIT
K/W
1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm
2
.
STATIC CHARACTERISTICS
T
j
= 25
°C
unless otherwise specified.
SYMBOL
V
(BR)DSS
I
GSS
V
GSth
R
DSon
I
DSS
Y
fs
C
iss
C
oss
C
rss
t
on
t
off
PARAMETER
drain-source breakdown voltage
gate-source leakage current
gate-source threshold voltage
drain-source on-state resistance
drain-source leakage current
transfer admittance
input capacitance
output capacitance
feedback capacitance
CONDITIONS
I
D
= 10
µA;
V
GS
= 0
V
GS
=
±20
V; V
DS
= 0
I
D
= 1 mA; V
DS
= V
GS
I
D
= 20 mA; V
GS
= 2.4 V
I
D
= 250 mA; V
GS
= 10 V
V
DS
= 240 V; V
GS
= 0
I
D
= 250 mA; V
DS
= 25 V
V
DS
= 25 V; V
GS
= 0; f = 1 MHz
V
DS
= 25 V; V
GS
= 0; f = 1 MHz
V
DS
= 25 V; V
GS
= 0; f = 1 MHz
I
D
= 250 mA; V
DD
= 50 V;
V
GS
= 0 to 10 V
I
D
= 250 mA; V
DD
= 50 V;
V
GS
= 10 to 0 V
MIN.
300
−
0.8
−
−
−
200
−
−
−
−
−
TYP. MAX. UNIT
−
−
−
4.8
3.7
−
690
100
21
10
−
±100
2
10
6
100
−
120
30
15
V
nA
V
Ω
Ω
nA
mS
pF
pF
pF
Switching times (see Figs
2
and
3)
turn-on time
turn-off time
6
46
10
60
ns
ns
2001 Dec 11
3
Philips Semiconductors
Product specification
N-channel enhancement mode
vertical D-MOS transistor
BSP130
handbook, halfpage
handbook, halfpage
VDD = 50 V
90 %
INPUT
10 %
90 %
10 V
0V
ID
50
Ω
MBB691
OUTPUT
10 %
ton
toff
MBB692
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
handbook, halfpage
2
MRC218
handbook, halfpage
250
MLD765
Ptot
(W)
1.5
C
(pF)
200
150
1
100
0.5
50
Coss
Crss
0
10
20
VDS (V)
30
Ciss
0
0
50
100
150
Tj (°C)
200
0
V
GS
= 0; f = 1 MHz; T
j
= 25
°C.
Fig.5
Fig.4 Power derating curve.
Capacitance as a function of drain-source
voltage; typical values.
2001 Dec 11
4
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