CY7C43662V-15AC datasheet, PDF

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CY7C43662V-15AC: DescriptionBi-Directional FIFO, 4KX36, 10ns, Synchronous, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-120; Categorystorage storage; File Size629KB，30 Pages; ManufacturerCypress Semiconductor

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CY7C43662V-15AC Overview

Bi-Directional FIFO, 4KX36, 10ns, Synchronous, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-120

CY7C43662V-15AC Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	QFP
package instruction	14 X 14 MM, 1.40 MM HEIGHT, TQFP-120
Contacts	120
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	10 ns
Other features	MAIL BOX; RETRANSMIT
Maximum clock frequency (fCLK)	67 MHz
period time	15 ns
JESD-30 code	S-PQFP-G120
JESD-609 code	e0
length	14 mm
memory density	147456 bit
Memory IC Type	BI-DIRECTIONAL FIFO
memory width	36
Number of functions	1
Number of terminals	120
word count	4096 words
character code	4000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4KX36
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP120,.63SQ,16
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum standby current	0.012 A
Maximum slew rate	0.06 mA
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	2.97 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.4 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

CY7C43662V-15AC Preview

PRELIMINARY

CY7C43642V

CY7C43662V/CY7C43682V

3.3V 1K/4K/16K x36 x2 Bidirectional

Synchronous FIFO

Features

• 3.3V high-speed, low-power, bidirectional, first-in

first-out (FIFO) memories

• 1K x36 x2 (CY7C43642V)

• 4K x36 x2 (CY7C43662V)

• 16K x36 x2 (CY7C43682V)

• 0.35-micron CMOS for optimum speed/power

• High-speed 67-MHz operation (15 ns read/write cycle

times)

• Low power

— I

= 60 mA

— I

= 5 mA

• Fully asynchronous and simultaneous read and write

operation permitted

• Mailbox bypass register for each FIFO

• Parallel Programmable Almost-Full and Almost-Empty

flags

• Retransmit function

• Standard or FWFT mode user selectable

• 120-pin TQFP packaging

• 3.3V pin-compatible, feature enhanced, density up-

grade to IDT723622/32/42 family

• Easily expandable in width and depth

Logic Block Diagram

MBF1

CLKA

CSA

W/RA

ENA

MBA

RT2

Port-A

Control

Logic

Input

Mail 1

1K/4K/16K

x36

Dual Ported

Memory

CLKB

CSB

W/RB

ENB

MBB

RT1

MRS1

PRS1

FIFO1,

Mail 1

Reset

Logic

Write

Pointer

Read

Pointer

FFA/IRA

AFA

Status

Flag Logic

Output

Port-B

Control

Logic

EFB/ORB

AEB

SPM

FS0/SD

FS1/SEN

0–35

EFA/ORA

AEA

Programmable Flag

Offset Registers

Timing

Mode

0–35

FWFT/STAN

Status

Flag Logic

Write

Pointer

Read

Pointer

FFB/IRB

AFB

Output

1K/4K/16K

x36

Dual Ported

Memory

Mail 2

MBF2

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

Input

FIFO2,

Mail 2

Reset

Logic

MRS2

PRS2

•

CA 95134

•

408-943-2600

October 2, 1998

PRELIMINARY

Pin Configuration

GND

CLKA

ENA

W/RA

CY7C43642V

CY7C43662V/CY7C43682V

TQFP

AEB

AFB

FFB/ORB

EFB/IRB

GND

CSB

W/RB

ENB

CLKB

CSA

EFA/IRA

FFA/ORA

AFA

AEA

MBF2

MBA

RST1

FS0

GND

FS1

Top View

RST2

MBB

MBF1

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

GND

FWFT/STAN

GND

RT2

104

103

102

101

100

GND

RT1

GND

CY7C43642V

CY7C43662V

CY7C43682V

GND

PRELIMINARY

Functional Description

The CY7C436X2V is a monolithic, high-speed, low-power,

CMOS Bidirectional Synchronous (clocked) FIFO memory

which supports clock frequencies up to 83 MHz and has read

access times as fast as 9 ns. Two independent 1K/4K/16K x

36 dual-port SRAM FIFOs on board each chip buffer data in

opposite directions.

The CY7C436X2V is a synchronous (clocked) FIFO, meaning

each port employs a synchronous interface. All data transfers

through a port are gated to the LOW-to-HIGH transition of a

port clock by enable signals. The clocks for each port are in-

dependent of one another and can be asynchronous or coin-

cident. The enables for each port are arranged to provide a

simple bidirectional interface between microprocessors and/or

buses with synchronous control.

Communication between each port may bypass the FIFOs via

two mailbox registers. The mailbox registers’ width matches

the selected Port B bus width. Each mailbox register has a flag

(MBF1 and MBF2) to signal when new mail has been stored.

Master Reset initializes the read and write pointers to the first

location of the memory array, and selects parallel flag pro-

gramming, or one of the three possible default flag offset set-

tings, 8, 16, or 64. Each FIFO has its own independent Master

Reset pin, MRS1 and MRS2.

The CY7C436X2V have two modes of operation: In the CY

Standard Mode, the first word written to an empty FIFO is de-

posited into the memory array. A read operation is required to

access that word (along with all other words residing in mem-

ory). In the First Word Fall Through Mode (FWFT), the first

word (36-bit wide) written to an empty FIFO appears automat-

ically on the outputs, no read operation required (nevertheless,

accessing subsequent words does necessitate a formal read

request). The state of the FWFT/STAN pin during FIFO oper-

ation determines the mode in use.

CY7C43642V

CY7C43662V/CY7C43682V

Each FIFO has a combined Empty/Output Ready flag

(EFA/ORA and EFB/ORB) and a combined Full/Input Ready

flag (FFA/IRA and FFB/IRB). The EF and FF functions are

selected in the CY Standard Mode. EF indicates whether the

memory is full or not. The IR and OR functions are selected in

the First Word Fall Through Mode. IR indicates whether or not

the FIFO has available memory locations. OR shows whether

the FIFO has data available for reading or not. It marks the

presence of valid data on the outputs.

Each FIFO has a programmable Almost Empty flag (AEA and

AEB) and a programmable Almost Full flag (AFA and AFB).

AEA and AEB indicate when a selected number of words writ-

ten to FIFO memory achieve a predetermined “almost empty

state.” AFA and AFB indicate when a selected number of

words written to the memory achieve a predetermined “almost

full state.”

IRA, IRB, AFA, and AFB are synchronized to the port clock that

writes data into its array. ORA, ORB, AEA, and AEB are syn-

chronized to the port clock that reads data from its array. Pro-

grammable offset for AEA, AEB, AFA, and AFB are loaded in

parallel using Port A or in serial via the SD input. Three default

offset settings are also provided. The AEA and AEB threshold

can be set at 8, 16, or 64 locations from the empty boundary

and AFA and AFB threshold can be set at 8, 16, or 64 locations

from the full boundary. All these choices are made using the

FS0 and FS1 inputs during Master Reset.

Two or more devices may be used in parallel to create wider

data paths. If at any time the FIFO is not actively performing a

function, the chip will automatically power down. During the

power down state, supply current consumption (I

) is at a

minimum. Initiating any operation (by activating control inputs)

will immediately take the device out of the Power Down state.

The CY7C436X2V are characterized for operation from 0°C to

70°C. Input ESD protection is greater than 2001V, and latch-up

is prevented by the use of guard rings.

Selection Guide

CY7C43642/62/82V–15

Maximum Frequency (MHz)

Maximum Access Time (ns)

Minimum Cycle Time (ns)

Minimum Data or Enable Set-Up (ns)

Minimum Data or Enable Hold (ns)

Maximum Flag Delay (ns)

Active Power Supply

Current (I

CC1

) (mA)

Commercial

Industrial

CY7C43642V

Density

Package

1K x 36 x2

120 TQFP

CY7C43662V

4K x 36 x2

120 TQFP

66.7

CY7C43682V

16K x 36 x2

120 TQFP

PRELIMINARY

Pin Definitions

Signal Name

0–35

AEA

Description

Port A Data

Port A Almost

Empty Flag

Port B Almost

Empty Flag

Port A Almost

Full Flag

Port B Almost

Full Flag

Port B Data

Big Endian/First

Word Fall

Through Select

Port A Clock

I/O

CY7C43642V

CY7C43662V/CY7C43682V

Function

36-bit bidirectional data port for side A.

Programmable almost-empty flag synchronized to CLKA. It is LOW when the number

of words in FIFO2 is less than or equal to the value in the almost-empty A offset register,

X2.

Programmable almost-empty flag synchronized to CLKB. It is LOW when the number

of words in FIFO1 is less than or equal to the value in the almost-empty B offset register,

X1.

Programmable almost-full flag synchronized to CLKA. It is LOW when the number of

empty locations in FIFO1 is less than or equal to the value in the almost-full A offset

Programmable almost-full flag synchronized to CLKB. It is LOW when the number of

empty locations in FIFO2 is less than or equal to the value in the almost-full B offset

36-bit bidirectional data port for side B.

During Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW selects

First Word Fall Through mode. Once the timing mode has been selected, the level on

FWFT/STAN must be static throughout device operation.

CLKA is a continuous clock that synchronizes all data transfers through Port A and can

be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all

synchronized to the LOW-to-HIGH transition of CLKA.

CLKB is a continuous clock that synchronizes all data transfers through Port B and can

be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all

synchronized to the LOW-to-HIGH transition of CLKB.

CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on

Port A. The A

0–35

outputs are in the high-impedance state when CSA is HIGH.

CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on

Port B. The B

0–35

outputs are in the high-impedance state when CSB is HIGH.

This is a dual-function pin. In the CY Standard Mode, the EFA function is selected. EFA

indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA

function is selected. ORA indicates the presence of valid data on A

0–35

outputs avail-

able for reading. FFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.

This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB

indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB

function is selected. ORB indicates the presence of valid data on B

0–35

outputs avail-

able for reading. FFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data

on Port A.

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data

on Port B.

This is a dual-function pin. In the CY Standard Mode, the FFA function is selected. FFA

indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function

is selected. IRA indicates whether or not there is space available for writing to the FIFO1

memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.

This is a dual-function pin. In the CY Standard Mode, the FFB function is selected. FFB

indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function

is selected. IRB indicates whether or not there is space available for writing to the FIFO2

memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.

AEB

AFA

AFB

0–35

FWFT/STAN

I/O

CLKA

CLKB

Port B Clock

CSA

CSB

EFA/ORA

Port A Chip

Select

Port B Chip

Select

Port A Empty/

Output Ready

Flag

Port B Empty/

Output Ready

Flag

Port A Enable

Port B Enable

Port A Full/Input

Ready Flag

EFB/ORB

ENA

ENB

FFA/IRA

FFB/IRB

Port B Full/Input

Ready Flag

PRELIMINARY

Pin Definitions

(continued)

Signal Name

FS1

FS0

Description

Flag Offset

Select 1

Flag Offset

Select 0

I/O

CY7C43642V

CY7C43662V/CY7C43682V

Function

FS1 and FS0 are dual-purpose inputs used for flag offset register programming. During

Master Reset, FS1 and FS0, together with SPM, select the flag offset programming

method. Three offset register programming methods are available: automatically load

one of three preset values (8, 16, or 64), parallel load from Port A, and serial load.

When serial load is selected for flag offset register programming, FS1 is used as an

enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1 is LOW, a

rising edge on CLKA loads the bit present on FS0/SD into the X and Y registers. The

number of bit writes required to program the offset registers is 40 for the CY7C43642V,

48 for the CY7C43662V, and 56 for the CY7C43682V. The first bit write stores the

Y-register MSB and the last bit write stores the X-register LSB.

A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.

When the A

0–35

outputs are active, a HIGH level on MBA selects data from the Mail2

A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.

When the B

0–35

outputs are active, a HIGH level on MBB selects data from the Mail1

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1

HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB

is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.

MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2

HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA

is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.

A LOW on this pin initializes the FIFO1 read and write pointers to the first location of

memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects

the programming method (serial or parallel) and one of three programmable flag default

offsets for FIFO1. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH tran-

sitions of CLKB must occur while MRS1 is LOW.

A LOW on this pin initializes the FIFO2 read and write pointers to the first location of

memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects

one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transi-

tions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is

LOW.

A HIGH selects a write operation and a LOW selects a read operation on Port A for a

LOW-to-HIGH transition of CLKA. The A

0–35

outputs are in the HIGH impedance state

when W/RA is HIGH.

A LOW selects a write operation and a HIGH selects a read operation on Port B for a

LOW-to-HIGH transition of CLKB. The B

0–35

outputs are in the HIGH impedance state

when W/RB is LOW.

MBA

Port A Mailbox

Select

Port B Mailbox

Select

Mail1 Register

Flag

MBB

MBF1

MBF2

Mail2 Register

Flag

MRS1

FIFO1 Master

Reset

MRS2

FIFO2 Master

Reset

W/RA

Port A

Write/Read

Select

Port B

Write/Read

Select

W/RB

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CY7C43662V-15AC Related Products

	CY7C43662V-15AC	CY7C43642V-15AC
Description	Bi-Directional FIFO, 4KX36, 10ns, Synchronous, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-120	Bi-Directional FIFO, 1KX36, 10ns, Synchronous, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-120
Is it Rohs certified?	incompatible	incompatible
Maker	Cypress Semiconductor	Cypress Semiconductor
Parts packaging code	QFP	QFP
package instruction	14 X 14 MM, 1.40 MM HEIGHT, TQFP-120	LFQFP, QFP120,.63SQ,16
Contacts	120	120
Reach Compliance Code	not_compliant	not_compliant
ECCN code	EAR99	EAR99
Maximum access time	10 ns	10 ns
Other features	MAIL BOX; RETRANSMIT	MAIL BOX; RETRANSMIT
Maximum clock frequency (fCLK)	67 MHz	67 MHz
period time	15 ns	15 ns
JESD-30 code	S-PQFP-G120	S-PQFP-G120
JESD-609 code	e0	e0
length	14 mm	14 mm
memory density	147456 bit	36864 bit
Memory IC Type	BI-DIRECTIONAL FIFO	BI-DIRECTIONAL FIFO
memory width	36	36
Number of functions	1	1
Number of terminals	120	120
word count	4096 words	1024 words
character code	4000	1000
Operating mode	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C
organize	4KX36	1KX36
Exportable	YES	YES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP
Encapsulate equivalent code	QFP120,.63SQ,16	QFP120,.63SQ,16
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm
Maximum standby current	0.012 A	0.012 A
Maximum slew rate	0.06 mA	0.06 mA
Maximum supply voltage (Vsup)	3.63 V	3.63 V
Minimum supply voltage (Vsup)	2.97 V	2.97 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.4 mm	0.4 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	14 mm	14 mm

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