V
PRELIMINARY
CY7C43642V
CY7C43662V/CY7C43682V
3.3V 1K/4K/16K x36 x2 Bidirectional
Synchronous FIFO
Features
• 3.3V high-speed, low-power, bidirectional, first-in
first-out (FIFO) memories
• 1K x36 x2 (CY7C43642V)
• 4K x36 x2 (CY7C43662V)
• 16K x36 x2 (CY7C43682V)
• 0.35-micron CMOS for optimum speed/power
• High-speed 67-MHz operation (15 ns read/write cycle
times)
• Low power
— I
CC
= 60 mA
— I
SB
= 5 mA
• Fully asynchronous and simultaneous read and write
operation permitted
• Mailbox bypass register for each FIFO
• Parallel Programmable Almost-Full and Almost-Empty
flags
• Retransmit function
• Standard or FWFT mode user selectable
• 120-pin TQFP packaging
• 3.3V pin-compatible, feature enhanced, density up-
grade to IDT723622/32/42 family
• Easily expandable in width and depth
Logic Block Diagram
MBF1
CLKA
CSA
W/RA
ENA
MBA
RT2
Port-A
Control
Logic
Input
Register
Mail 1
Register
1K/4K/16K
x36
Dual Ported
Memory
CLKB
CSB
W/RB
ENB
MBB
RT1
Register
MRS1
PRS1
FIFO1,
Mail 1
Reset
Logic
Write
Pointer
Read
Pointer
FFA/IRA
AFA
Status
Flag Logic
Output
Port-B
Control
Logic
EFB/ORB
AEB
SPM
FS0/SD
FS1/SEN
A
0–35
EFA/ORA
AEA
Programmable Flag
Offset Registers
Timing
Mode
B
0–35
FWFT/STAN
Status
Flag Logic
Write
Pointer
Read
Pointer
FFB/IRB
AFB
Output
Register
1K/4K/16K
x36
Dual Ported
Memory
Mail 2
Register
MBF2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
Input
Register
FIFO2,
Mail 2
Reset
Logic
MRS2
PRS2
•
CA 95134
•
408-943-2600
October 2, 1998
PRELIMINARY
Pin Configuration
GND
CLKA
ENA
W/RA
CY7C43642V
CY7C43662V/CY7C43682V
TQFP
AEB
AFB
FFB/ORB
EFB/IRB
GND
CSB
W/RB
ENB
CLKB
V
CC
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
CSA
EFA/IRA
FFA/ORA
V
CC
AFA
AEA
MBF2
MBA
RST1
FS0
GND
FS1
Top View
RST2
MBB
MBF1
V
CC
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
B
24
A
23
FWFT/STAN
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
RT2
A
12
104
103
102
101
100
99
98
97
96
95
94
93
92
91
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
RT1
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
CY7C43642V
CY7C43662V
CY7C43682V
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
A
8
A
7
A
6
GND
A
5
A
4
A
3
V
CC
A
2
A
1
A
0
GND
2
B
4
B
5
GND
B
6
V
CC
B
7
B
8
B
9
B
10
B
11
GND
A
11
A
10
A
9
B
0
B
1
B
2
B
3
47
48
49
50
51
52
53
54
55
56
57
58
59
60
PRELIMINARY
Functional Description
The CY7C436X2V is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous (clocked) FIFO memory
which supports clock frequencies up to 83 MHz and has read
access times as fast as 9 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions.
The CY7C436X2V is a synchronous (clocked) FIFO, meaning
each port employs a synchronous interface. All data transfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each port are in-
dependent of one another and can be asynchronous or coin-
cident. The enables for each port are arranged to provide a
simple bidirectional interface between microprocessors and/or
buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Master Reset initializes the read and write pointers to the first
location of the memory array, and selects parallel flag pro-
gramming, or one of the three possible default flag offset set-
tings, 8, 16, or 64. Each FIFO has its own independent Master
Reset pin, MRS1 and MRS2.
The CY7C436X2V have two modes of operation: In the CY
Standard Mode, the first word written to an empty FIFO is de-
posited into the memory array. A read operation is required to
access that word (along with all other words residing in mem-
ory). In the First Word Fall Through Mode (FWFT), the first
word (36-bit wide) written to an empty FIFO appears automat-
ically on the outputs, no read operation required (nevertheless,
accessing subsequent words does necessitate a formal read
request). The state of the FWFT/STAN pin during FIFO oper-
ation determines the mode in use.
CY7C43642V
CY7C43662V/CY7C43682V
Each FIFO has a combined Empty/Output Ready flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
flag (FFA/IRA and FFB/IRB). The EF and FF functions are
selected in the CY Standard Mode. EF indicates whether the
memory is full or not. The IR and OR functions are selected in
the First Word Fall Through Mode. IR indicates whether or not
the FIFO has available memory locations. OR shows whether
the FIFO has data available for reading or not. It marks the
presence of valid data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words writ-
ten to FIFO memory achieve a predetermined “almost empty
state.” AFA and AFB indicate when a selected number of
words written to the memory achieve a predetermined “almost
full state.”
IRA, IRB, AFA, and AFB are synchronized to the port clock that
writes data into its array. ORA, ORB, AEA, and AEB are syn-
chronized to the port clock that reads data from its array. Pro-
grammable offset for AEA, AEB, AFA, and AFB are loaded in
parallel using Port A or in serial via the SD input. Three default
offset settings are also provided. The AEA and AEB threshold
can be set at 8, 16, or 64 locations from the empty boundary
and AFA and AFB threshold can be set at 8, 16, or 64 locations
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths. If at any time the FIFO is not actively performing a
function, the chip will automatically power down. During the
power down state, supply current consumption (I
CC
) is at a
minimum. Initiating any operation (by activating control inputs)
will immediately take the device out of the Power Down state.
The CY7C436X2V are characterized for operation from 0°C to
70°C. Input ESD protection is greater than 2001V, and latch-up
is prevented by the use of guard rings.
Selection Guide
CY7C43642/62/82V–15
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
CC1
) (mA)
Commercial
Industrial
CY7C43642V
Density
Package
1K x 36 x2
120 TQFP
CY7C43662V
4K x 36 x2
120 TQFP
66.7
10
15
5
0
10
60
60
CY7C43682V
16K x 36 x2
120 TQFP
3
PRELIMINARY
Pin Definitions
Signal Name
A
0–35
AEA
Description
Port A Data
Port A Almost
Empty Flag
Port B Almost
Empty Flag
Port A Almost
Full Flag
Port B Almost
Full Flag
Port B Data
Big Endian/First
Word Fall
Through Select
Port A Clock
I/O
I/O
O
CY7C43642V
CY7C43662V/CY7C43682V
Function
36-bit bidirectional data port for side A.
Programmable almost-empty flag synchronized to CLKA. It is LOW when the number
of words in FIFO2 is less than or equal to the value in the almost-empty A offset register,
X2.
Programmable almost-empty flag synchronized to CLKB. It is LOW when the number
of words in FIFO1 is less than or equal to the value in the almost-empty B offset register,
X1.
Programmable almost-full flag synchronized to CLKA. It is LOW when the number of
empty locations in FIFO1 is less than or equal to the value in the almost-full A offset
register, Y1.
Programmable almost-full flag synchronized to CLKB. It is LOW when the number of
empty locations in FIFO2 is less than or equal to the value in the almost-full B offset
register, Y2.
36-bit bidirectional data port for side B.
During Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW selects
First Word Fall Through mode. Once the timing mode has been selected, the level on
FWFT/STAN must be static throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A and can
be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all
synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can
be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are all
synchronized to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on
Port A. The A
0–35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on
Port B. The B
0–35
outputs are in the high-impedance state when CSB is HIGH.
This is a dual-function pin. In the CY Standard Mode, the EFA function is selected. EFA
indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA
function is selected. ORA indicates the presence of valid data on A
0–35
outputs avail-
able for reading. FFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA.
This is a dual-function pin. In the CY Standard Mode, the EFB function is selected. EFB
indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB
function is selected. ORB indicates the presence of valid data on B
0–35
outputs avail-
able for reading. FFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data
on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data
on Port B.
This is a dual-function pin. In the CY Standard Mode, the FFA function is selected. FFA
indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function
is selected. IRA indicates whether or not there is space available for writing to the FIFO1
memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA.
This is a dual-function pin. In the CY Standard Mode, the FFB function is selected. FFB
indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function
is selected. IRB indicates whether or not there is space available for writing to the FIFO2
memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB.
AEB
O
AFA
O
AFB
O
B
0–35
FWFT/STAN
I/O
I
CLKA
I
CLKB
Port B Clock
I
CSA
CSB
EFA/ORA
Port A Chip
Select
Port B Chip
Select
Port A Empty/
Output Ready
Flag
Port B Empty/
Output Ready
Flag
Port A Enable
Port B Enable
Port A Full/Input
Ready Flag
I
I
O
EFB/ORB
O
ENA
ENB
FFA/IRA
I
I
O
FFB/IRB
Port B Full/Input
Ready Flag
O
4
PRELIMINARY
Pin Definitions
(continued)
Signal Name
FS1
FS0
Description
Flag Offset
Select 1
Flag Offset
Select 0
I/O
I
I
CY7C43642V
CY7C43662V/CY7C43682V
Function
FS1 and FS0 are dual-purpose inputs used for flag offset register programming. During
Master Reset, FS1 and FS0, together with SPM, select the flag offset programming
method. Three offset register programming methods are available: automatically load
one of three preset values (8, 16, or 64), parallel load from Port A, and serial load.
When serial load is selected for flag offset register programming, FS1 is used as an
enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1 is LOW, a
rising edge on CLKA loads the bit present on FS0/SD into the X and Y registers. The
number of bit writes required to program the offset registers is 40 for the CY7C43642V,
48 for the CY7C43662V, and 56 for the CY7C43682V. The first bit write stores the
Y-register MSB and the last bit write stores the X-register LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
When the A
0–35
outputs are active, a HIGH level on MBA selects data from the Mail2
register for output and a LOW level selects FIFO2 output register data for output.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation.
When the B
0–35
outputs are active, a HIGH level on MBB selects data from the Mail1
register for output and a LOW level selects FIFO1 output register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1
register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set
HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB
is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2
register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set
HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA
is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2.
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag default
offsets for FIFO1. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH tran-
sitions of CLKB must occur while MRS1 is LOW.
A LOW on this pin initializes the FIFO2 read and write pointers to the first location of
memory and sets the Port A output register to all zeroes. A LOW pulse on MRS2 selects
one of three programmable flag default offsets for FIFO2. Four LOW-to-HIGH transi-
tions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS2 is
LOW.
A HIGH selects a write operation and a LOW selects a read operation on Port A for a
LOW-to-HIGH transition of CLKA. The A
0–35
outputs are in the HIGH impedance state
when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on Port B for a
LOW-to-HIGH transition of CLKB. The B
0–35
outputs are in the HIGH impedance state
when W/RB is LOW.
MBA
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
I
MBB
I
MBF1
O
MBF2
Mail2 Register
Flag
O
MRS1
FIFO1 Master
Reset
I
MRS2
FIFO2 Master
Reset
I
W/RA
Port A
Write/Read
Select
Port B
Write/Read
Select
I
W/RB
I
5
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