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72V03L35JGI

Description
FIFO
Categorystorage    storage   
File Size250KB,13 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

72V03L35JGI Overview

FIFO

72V03L35JGI Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
Reach Compliance Codecompliant
3.3 VOLT CMOS ASYNCHRONOUS FIFO
IDT72V01, IDT72V02
IDT72V03, IDT72V04
IDT72V05, IDT72V06
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
8,192 x 9, 16,384 x 9
FEATURES:
3.3V family uses less power than the 5 Volt 7201/7202/7203/7204/
7205/7206 family
512 x 9 organization (72V01)
1,024 x 9 organization (72V02)
2,048 x 9 organization (72V03)
4,096 X 9 organization (72V04)
8,192 x 9 organization (72V05)
16,384 X 9 organization (72V06)
Functionally compatible with 720x family
Low-power consumption
— Active: 180 mW (max.)
— Power-down: 18 mW (max.)
15 ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
Available in 32-pin PLCC
Industrial temperature range (–40°C to +85°C) is available
°
°
Green parts available, see ordering information
DESCRIPTION:
The IDT72V01/72V02/72V03/72V04/72V05/72V06 are dual-port FIFO
memories that operate at a power supply voltage (Vcc) between 3.0V and 3.6V.
Their architecture, functional operation and pin assignments are identical to
those of the IDT7201/7202/7203/7204/7205/7206. These devices load and
empty data on a first-in/first-out basis. They use Full and Empty flags to prevent
data overflow and underflow and expansion logic to allow for unlimited
expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins. The devices have a maximum data access time as fast as 25 ns.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. They also feature a Retransmit (RT) capability that allows for
reset of the read pointer to its initial position when
RT
is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. It has
been designed for those applications requiring asynchronous and simultane-
ous read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
DATA INPUTS
(D
0-
D
8
)
W
WRITE
CONTROL
WRITE
POINTER
RAM
ARRAY
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
16,384 x 9
READ
POINTER
R
READ
CONTROL
THREE-
STATE
BUFFERS
DATA OUTPUTS
(Q
0-
Q
8
)
RS
RESET
LOGIC
FL/RT
FLAG
LOGIC
EXPANSION
LOGIC
EF
FF
XI
XO/HF
3033 drw 01
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2017
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2017
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