LPR200JC15 datasheet, PDF - EEWORLD Datasheet

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LPR200JC15: DescriptionPipeline Register, 16-Bit, CMOS, PQCC52, PLASTIC, LCC-52; CategoryThe embedded processor and controller Microcontrollers and processors; File Size249KB，8 Pages; ManufacturerLOGIC Devices; Websitehttp://www.logicdevices.com/

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LPR200JC15 Overview

Pipeline Register, 16-Bit, CMOS, PQCC52, PLASTIC, LCC-52

LPR200JC15 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	LOGIC Devices
Parts packaging code	LCC
package instruction	QCCJ, LDCC52,.8SQ
Contacts	52
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Other features	PROGRAMMABLE MULTILEVEL REGISTER CONFIGURATIONS; ICC SPECIFIED @ 10MHZ
boundary scan	NO
maximum clock frequency	66.67 MHz
External data bus width	16
JESD-30 code	S-PQCC-J52
JESD-609 code	e0
length	19.1262 mm
low power mode	NO
Humidity sensitivity level	3
Number of terminals	52
Maximum operating temperature	70 °C
Minimum operating temperature
Output data bus width	16
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC52,.8SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum slew rate	30 mA
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	19.1262 mm
uPs/uCs/peripheral integrated circuit type	DSP PERIPHERAL, PIPELINE REGISTER

LPR200JC15 Preview

LPR200

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

LPR200

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

DESCRIPTION

The

LPR200

is a programmable

multilevel pipeline register. This

device is pin-for-pin compatible with

the IDT73200.

The LPR200 contains eight 16-bit

high-speed pipeline registers which

can be configured as eight independent,

1-level pipelines; four independent,

2-level pipelines; two independent,

4-level pipelines; or as one 8-level

pipeline.

The Instruction pins, I

3-0

, control the

loading of the registers. The registers

can be configured as an eight-stage

delay line with data loaded into A

and shifted sequentially through B, C,

D, E, F, G and H as shown in Table 1.

The Instruction pins may also be set

to prevent any register from changing.

The Select lines, S

2-0

, control an 8-to-1

multiplexer which routes the contents

of any of the registers to the Y output

pins. The independence of the I and S

controls allow simultaneous write and

read operations on different registers.

FEATURES

u

Eight 16-bit High-Speed Pipeline

Registers

u

Programmable Multilevel Register

Configurations

u

Access time of 15 ns

Hold, Shift, and Load Instructions

Replaces IDT73200

52-pin PLCC, J-Lead

LPR200 B

LOCK

D

IAGRAM

C REG

D REG

A REG

B REG

A REG

MUX

B REG

C REG

D REG

MUX

E REG

F REG

OE

G REG

16

MUX

D

15-0

16

MUX

Y

15-0

H REG*

G REG

E REG

F REG

MUX

H REG

3

SEL

2-0

I

3-0

CLK

CEN

4

Pipeline Registers

1

08/16/2000–LDS.P200-C

LPR200

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

T

ABLE

1.

R

EGISTER

L

OAD

O

PERATIONS

Single 8-Level

Two 4-Level

SIGNAL DEFINITIONS

Power

V

CC

and GND

+5 V power supply. All pins must be

connected.

Clock

CLK — Master Clock

The rising edge of CLK strobes all

registers.

Inputs

D

15-0

— Data Input

16-bit data input port. Data is latched

into the registers on the rising edge of

CLK.

Outputs

Y

15-0

— Data Output

16-bit data output port.

Controls

I

3-0

— Instruction Control

The instruction control pins select

which register operation will be

carried out. Refer to Table 2.

A

B

C

D

E

F

G

H

A

B

C

D

E

F

G

H

Four 2-Level

Eight 1-Level

A

B

E

F

A

E

B

F

C

D

G

H

C

G

D

H

OE — Output Enable

SEL

2-0

— Output Select

The output select pins control which

register contents will appear at the

Y

15-0

output pins. Refer to Table 3.

CEN — Clock Enable

When CEN is LOW, the instruction

designated by I

3-0

is performed on the

registers. When CEN is HIGH, no

register operations are performed.

When OE is LOW, the register data

specified by SEL

2-0

is available on the

Y

15-0

output pins. When OE is HIGH,

the output port is in a high-impedance

state.

Pipeline Registers

2

08/16/2000–LDS.P200-C

LPR200

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

T

ABLE

3.

SEL

2

0

1

SEL

1

0

1

0

1

T

ABLE

2. LPR200 I

NSTRUCTION

T

ABLE

Inputs

Mnemonics

LDA

LDB

LDC

LDD

LDE

LDF

LDG

LDH

LSHAH

LSHAD

LSHEH

LSHAB

LSHCD

LSHEF

LSHGH

HOLD

I

3

0

1

I

2

0

1

0

1

I

1

0

1

0

1

0

1

0

1

I

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Description

D

15-0

©A

D

15-0

©B

D

15-0

©C

D

15-0

©D

D

15-0

©E

D

15-0

©F

D

15-0

©G

D

15-0

©H

D

15-0

©A

A©B B©C C©D D©E E©F F©G G©H

D

15-0

©A

A©B B©C C©D

D

15-0

©E

E©F F©G G©H

D

15-0

©A

A©B

D

15-0

©C

C©D

D

15-0

©E

E©F

D

15-0

©G

G©H

ALL REGISTERS ON HOLD

LPR200

O

UTPUT

S

ELECT

SEL

0

1

0

1

0

1

0

1

Y

15-0

A

B

C

D

E

F

G

H

Pipeline Registers

3

08/16/2000–LDS.P200-C

LPR200

DEVICES INCORPORATED

16-bit Multilevel Pipeline Register

M

AXIMUM

R

ATINGS

Above which useful life may be impaired (Notes 1, 2, 3, 8)

Storage temperature ........................................................................................................... –65°C to +155°C

Operating ambient temperature ........................................................................................... –55°C to +125°C

V

CC

supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V

Input signal with respect to ground ............................................................................... –0.5 V to V

CC

+ 0.5 V

Signal applied to high impedance output ...................................................................... –0.5 V to V

CC

+ 0.5 V

Output current into low outputs ............................................................................................................. 50 mA

Latchup current ............................................................................................................................... > 400 mA

O

PERATING

C

ONDITIONS

To meet specified electrical and switching characteristics

Mode

Active Operation, Commercial

Active Operation, Military

Temperature Range

(Ambient)

0°C to +70°C

–55°C to +125°C

Supply

Voltage

4.75 V

≤

V

CC

≤

5.25 V

4.50 V

≤

V

CC

≤

5.50 V

E

LECTRICAL

C

HARACTERISTICS

Over Operating Conditions (Note 4)

Symbol

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC1

I

CC2

C

IN

C

OUT

Parameter

Output High Voltage

Output Low Voltage

Input High Voltage

Input Low Voltage

Input Current

Output Leakage Current

V

CC

Current, Dynamic

V

CC

Current, Quiescent

Input Capacitance

Output Capacitance

(Note 3)

Test Condition

Vcc

= Min.,

I

OH

= –8.0 mA

Vcc

= Min.,

I

OL

= 16 mA

Min

2.4

Typ

Max

Unit

V

0.4

2.0

0.0

V

CC

0.8

±20

10

2.0

30

10

12

V

µA

mA

pF

Ground

≤

V

IN

≤

V

CC

(Note 12)

(Notes 5, 6)

(Note 7)

T

A

= 25°C, f = 1 MHz

T

A

= 25°C, f = 1 MHz

Pipeline Registers

4

08/16/2000–LDS.P200-C

432109876543210987654321

*D

ISCONTINUED

S

PEED

G

RADE

DEVICES INCORPORATED

C

OMMERCIAL

O

PERATING

R

ANGE

(0°C to +70°C)

Notes 9, 10 (ns)

SWITCHING CHARACTERISTICS

16-bit Multilevel Pipeline Register

LPR200–

15

210987654321

Min

210987654321

Min

S

WITCHING

W

AVEFORMS

Symbol

t

ENA

t

DIS

t

HC

t

SC

t

HD

t

SD

t

HI

t

SI

t

SEL

t

PD

t

PW

t

CYC

SEL

2-0

D

15-0

Y

15-0

CLK

OE

I

3-0

Parameter

Three-State Output Enable Delay

(Note 11)

Three-State Output Disable Delay

(Note 11)

Clock Enable Hold Time

Clock Enable Setup Time

Data Hold Time

Data Setup Time

Instruction Hold Time

Instruction Setup Time

Select to Output Delay

Clock to Output Delay

Clock Pulse Width

Cycle Time

t

SD

t

SI

t

SEL

t

HD

t

HI

t

PD

5

t

DIS

t

PW

HIGH IMPEDANCE

20

5

2

4

5

2

5

20*

t

PW

Max

15

10

20

t

ENA

Pipeline Registers

Min

15

5

2

4

5

2

5

Max

15

10

15

9

08/16/2000–LDS.P200-C

LPR200

12

5

2

3

4

1

2

5

12*

Max

12

9

8

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