M1AGL250V2-QNG132I datasheet, PDF

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M1AGL250V2-QNG132I: DescriptionField Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-132; CategoryProgrammable logic devices Programmable logic; File Size11MB，250 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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M1AGL250V2-QNG132I Overview

Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-132

M1AGL250V2-QNG132I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Microsemi
package instruction	VQCCN,
Reach Compliance Code	compliant
JESD-30 code	S-PBCC-B132
length	8 mm
Humidity sensitivity level	3
Equivalent number of gates	250000
Number of terminals	132
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	250000 GATES
Package body material	PLASTIC/EPOXY
encapsulated code	VQCCN
Package shape	SQUARE
Package form	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified
Maximum seat height	0.8 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BUTT
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	8 mm

M1AGL250V2-QNG132I Preview

Revision 23

IGLOO Low Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

•

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

5 µW Power Consumption in Flash*Freeze Mode

Low Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

• 15K to 1 Million System Gates

• Up to 144 Kbits of True Dual-Port SRAM

• Up to 300 User I/Os

•

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X

†

and LVCMOS 2.5 V / 5.0 V Input

†

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

• Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

• Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

‡

• Programmable Output Slew Rate

†

and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

†

• Six CCC Blocks, One with an Integrated PLL

• Configurable Phase Shift, Multiply/Divide, Delay Capabilities,

and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit

†

RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

• True Dual-Port SRAM (except ×18)

†

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

AGL250

M1AGL250

250,000

2,048

6,144

Yes

143

CS81, CS196

QN132

5,6

VQ100

FG144

FG144, FG256, FG144, FG256, FG144, FG256,

FG484

High Capacity

Reprogrammable Flash Technology

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Instant On Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

High-Performance Routing Hierarchy

Advanced I/O

• ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption (except ARM

-enabled IGLOO

devices) via

JTAG (IEEE 1532–compliant)

†

• FlashLock

Designed to Secure FPGA Contents

• Segmented, Hierarchical Routing and Clock Structure

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Embedded Memory

ARM Processor Support in IGLOO FPGAs

IGLOO Devices

AGL015

ARM-Enabled IGLOO Devices

System Gates

15,000

Typical Equivalent Macrocells

128

VersaTiles (D-flip-flops)

384

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

–

4,608-Bit Blocks

–

FlashROM Kbits (1,024 bits)

AES-Protected ISP

–

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

UC/CS

QFN

VQFP

FBGA

QN68

AGL030

30,000

256

768

–

AGL060 AGL125

60,000

512

1,536

Yes

125,000

1,024

3,072

Yes

133

CS196

QN132

VQ100

FG144

AGL400

400,000

–

9,216

Yes

194

CS196

AGL600

M1AGL600

600,000

–

13,824

108

Yes

235

CS281

AGL1000

M1AGL1000

1,000,000

–

24,576

144

Yes

300

CS281

UC81

CS121

CS81

QN48, QN68, QN132

QN132

VQ100

FG144

Notes:

AGL015 is not recommended for new designs

AES is not available for ARM-enabled IGLOO devices.

AGL060 in CS121 does not support the PLL.

Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

The M1AGL250 device does not support this package.

Device/package support TBD.

The

IGLOOe

datasheet and

IGLOOe FPGA Fabric User’s Guide

provide information on higher densities and additional features.

† AGL015 and AGL030 devices do not support this feature.

December 2012

‡ Supported only by AGL015 and AGL030 devices.

IGLOO Low Power Flash FPGAs

I/Os Per Package

IGLOO Devices

ARM-Enabled

IGLOO Devices

AGL015

AGL030 AGL060

AGL125

AGL250

M1AGL250

I/O

Single-Ended I/O

Type

Differential I/O Pairs

–

FG484

529

1.0

2.23

Single-Ended I/O

–

177

215

300

FG256

289

1.0

1.60

AGL400

AGL600

M1AGL600

AGL1000

M1AGL1000

Package

QN48

QN68

UC81

CS81

CS121

VQ100

QN132

CS196

FG144

FG256

CS281

FG484

–

133

–

5,6

143

–

5,6

–

143

178

–

194

–

177

215

235

–

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the

IGLOO FPGA Fabric User’s Guide

ensure compliance with design and board migration requirements.

2. AGL015 is not recommended for new designs.

3. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-

ended user I/Os available is reduced by one.

4. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

5. The M1AGL250 device does not support QN132 or CS196 packages.

6. Device/package support TBD.

7. FG256 and FG484 are footprint-compatible packages.

Table 1 • IGLOO FPGAs Package Sizes Dimensions

Package

Length × Width

(mm\mm)

Nominal Area

(mm

)

Pitch (mm)

Height (mm)

UC81

4×4

0.4

0.80

CS81

0.5

0.80

CS121

6×6

0.5

0.99

QN48

6×6

0.4

0.90

QN68

8×8

0.4

0.90

QN132

8×8

0.5

0.75

CS196

8×8

0.5

1.20

CS281

FG144

VQ100

10 × 10 13 × 13 14 × 14

100

0.5

1.05

169

1.0

1.45

196

0.5

1.00

17 × 17 23 × 23

R evis i o n 23

IGLOO Low Power Flash FPGAs

IGLOO Ordering Information

AGL1000

144

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I = Industrial (

–

40°C to +85°C Ambient Temperature)

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

Security Feature

Y = Device Includes License to Implement IP Based on the

Cryptography Research, Inc. (CRI) Patent Portfolio

Blank = Device Does Not Include License to Implement IP Based

on the Cryptography Research, Inc. (CRI) Patent Portfolio

Package Lead Count

Lead-Free Packaging

Blank = Standard Packaging

G= RoHS-Compliant Packaging (some packages also halogen-free)

Package Type

UC = Micro Chip Scale Package (0.4 mm pitch)

CS = Chip Scale Package (0.4 mm and 0.5 mm pitches)

QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch)

VQ = Very Thin Quad Flat Pack (0.5 mm pitch)

FG = Fine Pitch Ball Grid Array (1.0 mm pitch)

Supply Voltage

2 = 1.2 V to 1.5 V

5 = 1.5 V only

Part Number

IGLOO Devices

AGL015 = 15,000 System Gates

AGL030 = 30,000 System Gates

AGL060 = 60,000 System Gates

AGL125 = 125,000 System Gates

AGL250 = 250,000 System Gates

AGL400 = 400,000 System Gates

AGL600 = 600,000 System Gates

AGL1000 = 1,000,000 System Gates

IGLOO Devices with Cortex-M1

M1AGL250 = 250,000 System Gates

M1AGL600 = 600,000 System Gates

M1AGL1000 = 1,000,000 System Gates

Note:

Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly.

R ev i si o n 2 3

III

IGLOO Low Power Flash FPGAs

Temperature Grade Offerings

AGL015

Package

QN48

QN68

UC81

CS81

CS121

VQ100

QN132

CS196

FG144

FG256

CS281

FG484

–

C, I

–

C, I

–

C, I

–

C, I

–

C, I

–

C, I

–

C, I

–

AGL030

AGL060

AGL125

AGL250

M1AGL250

–

C, I

–

C, I

–

C, I

–

C, I

AGL400

AGL600

–

C, I

AGL1000

–

C, I

M1AGL600 M1AGL1000

Notes:

1. AGL015 is not recommended for new designs.

2. Device/package support TBD.

C = Commercial temperature range: 0°C to 70°C ambient temperature.

I = Industrial temperature range: –40°C to 85°C ambient temperature.

IGLOO Device Status

IGLOO Devices

AGL015

AGL030

AGL060

AGL125

AGL250

AGL400

AGL600

AGL1000

Status

Not recommended for new designs.

Production

M1AGL600

M1AGL1000

Production

M1AGL250

Production

M1 IGLOO Devices

Status

References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1

(Cortex-M1).

Contact your local Microsemi SoC Products Group representative for device availability:

www.microsemi.com/soc/contact/default.aspx.

AGL015 and AGL030

The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features.

Devices Not Recommended For New Designs

AGL015 is not recommended for new designs.

R evis i o n 23

IGLOO Low Power Flash FPGAs

Table of Contents

IGLOO Device Family Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

IGLOO DC and Switching Characteristics

General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1

Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

Power Calculation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17

User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20

VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-98

Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-104

Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-113

Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-116

Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-130

JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131

Pin Descriptions

Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-1

3-2

3-4

3-5

Package Pin Assignments

UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1

CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

CS196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9

CS281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16

QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23

QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25

QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-28

VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-37

FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-42

FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-55

FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-65

Datasheet Information

List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1

Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12

R ev i si o n 2 3

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M1AGL250V2-QNG132I Related Products

	M1AGL250V2-QNG132I	M1AGL250V2-QN132I	M1AGL250V2-QN132	M1AGL250V2-QNG132	M1AGL250V5-QN132I	M1AGL250V5-QN132	M1AGL250V5-QNG132I	M1AGL250V5-QNG132
Description	Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-132	Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132	Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132	Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-132	Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132	Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132	Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-132	Field Programmable Gate Array, 250000 Gates, CMOS, PBCC132, 8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, QFN-132
Is it Rohs certified?	conform to	incompatible	incompatible	conform to	incompatible	incompatible	conform to	conform to
Maker	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi	Microsemi
package instruction	VQCCN,	8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132	8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132	VQCCN,	8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132	8 X 8 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, QFN-132	VQCCN,	VQCCN,
Reach Compliance Code	compliant	unknown	unknown	compliant	unknown	unknown	compliant	compliant
JESD-30 code	S-PBCC-B132	S-PBCC-B132	S-PBCC-B132	S-PBCC-B132	S-PBCC-B132	S-PBCC-B132	S-PBCC-B132	S-PBCC-B132
length	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm
Equivalent number of gates	250000	250000	250000	250000	250000	250000	250000	250000
Number of terminals	132	132	132	132	132	132	132	132
Maximum operating temperature	85 °C	85 °C	70 °C	70 °C	85 °C	70 °C	85 °C	70 °C
organize	250000 GATES	250000 GATES	250000 GATES	250000 GATES	250000 GATES	250000 GATES	250000 GATES	250000 GATES
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	VQCCN	VQCCN	VQCCN	VQCCN	VQCCN	VQCCN	VQCCN	VQCCN
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER	CHIP CARRIER
Peak Reflow Temperature (Celsius)	260	235	235	260	235	235	260	260
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY	FIELD PROGRAMMABLE GATE ARRAY
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Maximum supply voltage	1.26 V	1.26 V	1.26 V	1.26 V	1.575 V	1.575 V	1.575 V	1.575 V
Minimum supply voltage	1.14 V	1.14 V	1.14 V	1.14 V	1.425 V	1.425 V	1.425 V	1.425 V
Nominal supply voltage	1.2 V	1.2 V	1.2 V	1.2 V	1.5 V	1.5 V	1.5 V	1.5 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL
Terminal form	BUTT	BUTT	BUTT	BUTT	BUTT	BUTT	BUTT	BUTT
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	30	20	20	30	20	20	30	30
width	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm	8 mm

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