HT12D/HT12F
2
12
Series of Decoders
Features
·
Operating voltage: 2.4V~12V
·
Low power and high noise immunity CMOS
·
Built-in oscillator needs only 5% resistor
·
Valid transmission indicator
·
Easy interface with an RF or an infrared transmission
technology
·
Low standby current
·
Capable of decoding 12 bits of information
·
Binary address setting
·
Received codes are checked 3 times
·
Address/Data number combination
-
HT12D: 8 address bits and 4 data bits
-
HT12F: 12 address bits only
medium
·
Minimal external components
·
Pair with Holtek¢s 2
12
series of encoders
·
18-pin DIP, 20-pin SOP package
Applications
·
Burglar alarm system
·
Smoke and fire alarm system
·
Garage door controllers
·
Car door controllers
·
Car alarm system
·
Security system
·
Cordless telephones
·
Other remote control systems
General Description
The 2
12
decoders are a series of CMOS LSIs for remote
control system applications. They are paired with
Holtek¢s 2
12
series of encoders (refer to the encoder/de-
coder cross reference table). For proper operation, a
pair of encoder/decoder with the same number of ad-
dresses and data format should be chosen.
The decoders receive serial addresses and data from a
programmed 2
12
series of encoders that are transmitted
by a carrier using an RF or an IR transmission medium.
They compare the serial input data three times continu-
ously with their local addresses. If no error or un-
matched codes are found, the input data codes are
decoded and then transferred to the output pins. The VT
pin also goes high to indicate a valid transmission.
The 2
12
series of decoders are capable of decoding
informations that consist of N bits of address and 12-N
bits of data. Of this series, the HT12D is arranged to pro-
vide 8 address bits and 4 data bits, and HT12F is used to
decode 12 bits of address information.
Selection Table
Function
Part No.
HT12D
HT12F
Address
No.
8
12
Data
No.
4
0
Type
L
¾
VT
Ö
Ö
Oscillator
RC oscillator
RC oscillator
Trigger
DIN active
²Hi²
DIN active
²Hi²
Package
18DIP, 20SOP
18DIP, 20SOP
Notes: Data type: L stands for latch type data output.
VT can be used as a momentary data output.
Rev. 1.20
1
February 20, 2009
HT12D/HT12F
Block Diagram
O S C 2
O S C 1
O s c illa to r
D iv id e r
D a ta S h ift
R e g is te r
L a tc h C ir c u it
D a ta
D IN
B u ffe r
D a ta D e te c to r
S y n c . D e te c to r
C o m p a ra to r
C o m p a ra to r
C o n tr o l L o g ic
T r a n s m is s io n G a te C ir c u it
B u ffe r
V T
A d d re s s
V D D
V S S
Note: The address/data pins are available in various combinations (see the address/data table).
Pin Assignment
8 -A d d re s s
4 -D a ta
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
V S S
9
8
7
6
5
4
3
2
1
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
V D D
V T
O S C 1
O S C 2
D IN
D 1 1
D 1 0
D 9
D 8
8 -A d d re s s
4 -D a ta
N C
1
2
3
4
5
6
7
8
9
1 0
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
V S S
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
N C
V D D
V T
O S C 1
O S C 2
D IN
D 1 1
D 1 0
D 9
D 8
1 2 -A d d re s s
0 -D a ta
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
V S S
9
8
7
6
5
4
3
2
1
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
V D D
V T
O S C 1
O S C 2
D IN
A 1 1
A 1 0
A 9
A 8
1 2 -A d d re s s
0 -D a ta
N C
1
2
3
4
5
6
7
8
9
1 0
A 0
A 1
A 2
A 3
A 4
A 5
A 6
A 7
V S S
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
N C
V D D
V T
O S C 1
O S C 2
D IN
A 1 1
A 1 0
A 9
A 8
H T 1 2 D
1 8 D IP -A
H T 1 2 D
2 0 S O P -A
H T 1 2 F
1 8 D IP -A
H T 1 2 F
2 0 S O P -A
Pin Description
Pin Name
A0~A11 (HT12F)
I
A0~A7 (HT12D)
D8~D11 (HT12D)
DIN
VT
OSC1
OSC2
VSS
VDD
O
I
O
I
O
¾
¾
CMOS OUT
CMOS IN
CMOS OUT
Oscillator
Oscillator
¾
¾
NMOS
Transmission Gate
I/O
Internal
Connection
Description
Input pins for address A0~A11 setting
These pins can be externally set to VSS or left open.
Input pins for address A0~A7 setting
These pins can be externally set to VSS or left open.
Output data pins, power-on state is low.
Serial data input pin
Valid transmission, active high
Oscillator input pin
Oscillator output pin
Negative power supply, ground
Positive power supply
Rev. 1.20
2
February 20, 2009
HT12D/HT12F
Approximate internal connection circuits
N M O S
T r a n s m is s io n G a te
C M O S O U T
C M O S IN
O s c illa to r
E N
O S C 1
O S C 2
Absolute Maximum Ratings
Supply Voltage ..........................................-0.3V to 13V
Input Voltage ................................V
SS
-0.3
to V
DD
+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-20°C to 75°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
Electrical Characteristics
Symbol
V
DD
I
STB
I
DD
I
O
Parameter
Operating Voltage
Standby Current
12V
Operating Current
Data Output Source Current (D8~D11)
Data Output Sink Current (D8~D11)
I
VT
V
IH
V
IL
f
OSC
VT Output Source Current
5V
VT Output Sink Current
²H²
Input Voltage
²L²
Input Voltage
Oscillator Frequency
5V
5V
5V
5V
5V
5V
No load, f
OSC
=150kHz
V
OH
=4.5V
V
OL
=0.5V
V
OH
=4.5V
V
OL
=0.5V
¾
¾
R
OSC
=51kW
Test Conditions
V
DD
¾
5V
Oscillator stops
Conditions
¾
Min.
2.4
¾
¾
¾
-1
1
-1
1
3.5
0
¾
Typ.
5
0.1
2
200
-1.6
1.6
-1.6
1.6
¾
¾
150
Max.
12
1
4
400
¾
¾
¾
¾
5
1
¾
Ta=25°C
Unit
V
mA
mA
mA
mA
mA
mA
mA
V
V
kHz
Rev. 1.20
3
February 20, 2009
HT12D/HT12F
Functional Description
Operation
The 2
12
series of decoders provides various combina-
tions of addresses and data pins in different packages
so as to pair with the 2
12
series of encoders.
The decoders receive data that are transmitted by an
encoder and interpret the first N bits of code period as
addresses and the last 12-N bits as data, where N is the
address code number. A signal on the DIN pin activates
the oscillator which in turn decodes the incoming ad-
dress and data. The decoders will then check the re-
ceived address three times continuously. If the received
address codes all match the contents of the decoder¢s
local address, the 12-N bits of data are decoded to acti-
vate the output pins and the VT pin is set high to indicate
a valid transmission. This will last unless the address
code is incorrect or no signal is received.
The output of the VT pin is high only when the transmis-
sion is valid. Otherwise it is always low.
Output Type
Of the 2
12
series of decoders, the HT12F has no data
output pin but its VT pin can be used as a momentary
data output. The HT12D, on the other hand, provides 4
latch type data pins whose data remain unchanged until
new data are received.
Part
No.
HT12D
HT12F
Data
Pins
4
0
Address
Pins
8
12
Output
Type
Latch
¾
Operating
Voltage
2.4V~12V
2.4V~12V
N o
Flowchart
The oscillator is disabled in the standby state and acti-
vated when a logic
²high²
signal applies to the DIN pin.
That is to say, the DIN should be kept low if there is no
signal input.
P o w e r o n
S ta n d b y m o d e
D is a b le V T &
ig n o r e th e r e s t o f
th is w o r d
N o
C o d e in ?
Y e s
A d d r e s s b its
m a tc h e d ?
Y e s
S to re d a ta
N o
M a tc h
p r e v io u s s to r e d
d a ta ?
Y e s
3 tim e s
o f c h e c k in g
c o m p le te d ?
Y e s
L a tc h d a ta
to o u tp u t &
a c tiv a te V T
N o
A d d re s s o r
d a ta e rro r ?
Y e s
N o
Decoder Timing
E n c o d e r
T r a n s m is s io n
E n a b le
E n c o d e r
D O U T
4 w o rd s
2
D e c o d e r V T
c h e c k
L a tc h e d
D a ta O u t
c h e c k
1 4
< 1 w o rd
c lo c k s
T r a n s m itte d
C o n tin u o u s ly
4 w o rd s
2
1 4
c lo c k s
Rev. 1.20
4
February 20, 2009
HT12D/HT12F
Encoder/Decoder Cross Reference Table
Package
Decoders
Part No.
Data Pins
Address Pins
VT
Pair Encoder
Encoder
DIP
HT12D
HT12F
4
0
8
12
Ö
Ö
HT12A
HT12E
HT12A
HT12E
18
18
SOP
20
20
Decoder
DIP
18
18
SOP
20
20
Address/Data Sequence
The following table provides address/data sequence for various models of the 2
12
series of decoders.
Part No.
HT12D
HT12F
Address/Data Bits
0
A0
A0
1
A1
A1
2
A2
A2
3
A3
A3
4
A4
A4
5
A5
A5
6
A6
A6
7
A7
A7
8
D8
A8
9
D9
A9
10
D10
A10
11
D11
A11
Oscillator Frequency Vs Supply Voltage
fo s c
(S c a le )
4 .0 0
R o s c (
9
)
2 7 k
9
3 .5 0
3 0 k
9
3 3 k
9
3 6 k
9
3 9 k
9
2 .5 0
4 3 k
9
4 7 k
9
5 1 k
9
2 .0 0
5 6 k
9
6 2 k
9
6 8 k
9
7 5 k
9
1 .5 0
8 2 k
9
1 0 0 k
9
(1 0 0 k H z )1 .0 0
1 2 0 k
9
1 5 0 k
9
1 8 0 k
9
0 .5 0
0 .2 5
2 2 0 k
9
3 .0 0
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
V D D
(V D C )
Note:
The recommended oscillator frequency is f
OSCD
(decoder)
@
50 f
OSCE
(HT12E encoder)
1
@
f
OSCE
(HT12A encoder).
3
Rev. 1.20
5
February 20, 2009
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