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PUMA68S4000XI-15

Description
SRAM Module, 128KX32, 15ns, CMOS, PQMA68, PLASTIC, LCC-68
Categorystorage    storage   
File Size482KB,8 Pages
ManufacturerAPTA Group Inc
Download Datasheet Parametric View All

PUMA68S4000XI-15 Overview

SRAM Module, 128KX32, 15ns, CMOS, PQMA68, PLASTIC, LCC-68

PUMA68S4000XI-15 Parametric

Parameter NameAttribute value
MakerAPTA Group Inc
Parts packaging codeQMA
package instructionQCCJ, LDCC68,1.0SQ
Contacts68
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time15 ns
Other featuresCAN ALSO BE CONFIGURED AS 512K X 8
Spare memory width16
I/O typeCOMMON
JESD-30 codeS-PQMA-J68
memory density4194304 bit
Memory IC TypeSRAM MODULE
memory width32
Number of functions1
Number of terminals68
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX32
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formMICROELECTRONIC ASSEMBLY
Parallel/SerialPARALLEL
power supply5 V
Certification statusNot Qualified
Maximum standby current0.26 A
Minimum standby current4.5 V
Maximum slew rate0.84 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
128K x 32 SRAM MODULE
PUMA 68S4000X - 12/15/20/25
Elm Road, West Chirton Industrial Estate, North Shields,
NE29 8SE, ENGLAND. TEL +44 (0191) 2930500. FAX +44 (0191)
2590997
Issue 1.5 : December 1998
Features
• Very Fast Access Times of 12/15/20/25 ns.
• JEDEC 68 'J' leaded plastic surface mount Substrate
• Upgradeable footprint.
• User Configurable as 8 / 16 / 32 bit wide output.
• Operating Power
Low Power Standby
-L Version
• Fully Static operation.
• Multiple ground pins for maximum noise immunity.
• Single 5V±10% Power supply.
(32-BIT)
(TTL)
(CMOS)
4.40 W (Max)
1.32 W (Max)
44 mW (Max)
Description
The PUMA68S4000X is a 4Mbit CMOS High Speed
Static RAM organised as 128K x 32 in a JEDEC 68
pin surface mount PLCC, available with access
times of 15ns, 20ns, or 25ns. The output width is user
configurable as 8 , 16 or 32 bits using four Chip
Selects (CS1~4).
The device features low power standby, multiple
ground pins for maximum noise immunity and TTL
compatible inputs and outputs. The PUMA
68S4000X offers a dramatic space saving
advantage over four standard 128Kx8 devices. A low
power standby option with 2V data retention mode is
available.
Block Diagram
A0-A16
OE
WE
128Kx8
SRAM
CS1
CS2
CS3
CS4
D0-7
D8-15
D16-23
D24-31
128Kx8
SRAM
128Kx8
SRAM
128Kx8
SRAM
Pin Definition
D16
NC
NC
CS4
CS3
CS2
CS1
NC
VCC
NC
NC
OE
WE
A16
A15
A14
D15
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
D17
D18
D19
VSS
D20
D21
D22
D23
VCC
D24
D25
D26
D27
VSS
D28
D29
D30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68S4000X
VIEW
FROM
ABOVE
55
54
53
52
51
50
49
48
47
46
45
44
D14
D13
D12
VSS
D11
D10
D9
D8
VCC
D7
D6
D5
D4
VSS
D3
D2
D1
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 - A16
D0 - D31
CS1~4
WE
OE
NC
V
CC
GND
Package Details
Plastic 68 J-Leaded JEDEC PLCC
D31
A6
A5
A4
A3
A2
A1
A0
VCC
A13
A12
A11
A10
A9
A8
A7
D0

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