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UT9Q512-ICC

Description
Standard SRAM, 512KX8, 25ns, CMOS, BOTTOM BRAZED, FP-36
Categorystorage    storage   
File Size276KB,16 Pages
ManufacturerCobham Semiconductor Solutions
Download Datasheet Parametric View All

UT9Q512-ICC Overview

Standard SRAM, 512KX8, 25ns, CMOS, BOTTOM BRAZED, FP-36

UT9Q512-ICC Parametric

Parameter NameAttribute value
MakerCobham Semiconductor Solutions
Parts packaging codeDFP
package instructionDFP,
Contacts36
Reach Compliance Codeunknown
ECCN code3A001.A.2.C
Maximum access time25 ns
JESD-30 codeR-XDFP-F36
length23.368 mm
memory density4194304 bit
Memory IC TypeSTANDARD SRAM
memory width8
Number of functions1
Number of terminals36
word count524288 words
character code512000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize512KX8
Package body materialUNSPECIFIED
encapsulated codeDFP
Package shapeRECTANGULAR
Package formFLATPACK
Parallel/SerialPARALLEL
Certification statusNot Qualified
Maximum seat height4.4196 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationDUAL
width12.192 mm
Standard Products
Data Sheet
February, 2003
QCOTS
TM
UT9Q512 512K x 8 SRAM
FEATURES
20ns maximum (5 volt supply) address access time
Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
TTL compatible inputs and output levels, three-state
bidirectional data bus
Typical radiation performance
- Total dose: 50krads
- >100krads(Si), for any orbit, using Aeroflex UTMC
patented shielded package
- SEL Immune >80 MeV-cm
2
/mg
- LET
TH
(0.25) = >10 MeV-cm
2
/mg
- Saturated Cross Section (cm
2
) per bit, 5.0E-9
-<1E-8 errors/bit-day, Adams to 90% geosynchronous
heavy ion
Packaging options:
- 36-lead ceramic flatpack (weight 3.42 grams)
- 36-lead flatpack shielded (weight 10.77 grams)
Standard Microcircuit Drawing 5962-00536
- QML T and Q compliant part
INTRODUCTION
The QCOTS
TM
UT9Q512 Quantified Commercial Off-the-
Shelf product is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (E), an active LOW
Output Enable (G), and three-state drivers. This device has a
power-down feature that reduces power consumption by more
than 90% when deselected
.
Writing to the device is accomplished by taking Chip Enable
one (E) input LOW and Write Enable (W) inputs LOW. Data on
the eight I/O pins (DQ
0
through DQ
7
) is then written into the
location specified on the address pins (A
0
through A
18
). Reading
from the device is accomplished by taking Chip Enable one (E)
and Output Enable (G) LOW while forcing Write Enable (W)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input/output pins (DQ
0
through DQ
7
) are placed in a
high impedance state when the device is deselected (E) HIGH),
the outputs are disabled (G HIGH), or during a write operation
(E LOWand W LOW).
Clk. Gen.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Pre-Charge Circuit
Row Select
Memory Array
1024 Rows
512x8 Columns
I/O Circuit
Column Select
Data
Control
CLK
Gen.
A10
A11
A12
A13
A14
A15
A16
A17
A18
DQ
0
- DQ
7
E
W
G
Figure 1. UT9Q512 SRAM Block Diagram
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