Features
•
Fast Read Access Time – 120 ns
•
Fast Byte Write – 200 µs or 1 ms
•
Self-timed Byte Write Cycle
– Internal Address and Data Latches
– Internal Control Timer
– Automatic Clear Before Write
Direct Microprocessor Control
– READY/BUSY Open Drain Output
– DATA Polling
Low Power
– 30 mA Active Current
– 100 µA CMOS Standby Current
High Reliability
– Endurance: 10
4
or 10
5
Cycles
– Data Retention: 10 Years
5V
±
10% Supply
CMOS and TTL Compatible Inputs and Outputs
JEDEC Approved Byte-wide Pinout
Commercial and Industrial Temperature Ranges
•
•
•
•
•
•
•
64K (8K x 8)
Parallel
EEPROMs
AT28C64
AT28C64X
Description
The AT28C64 is a low-power, high-performance 8,192 words by 8-bit nonvolatile elec-
trically erasable and programmable read only memory with popular, easy-to-use fea-
tures. The device is manufactured with Atmel’s reliable nonvolatile technology.
(continued)
Pin Configurations
Pin Name
A0 - A12
CE
OE
WE
I/O0 - I/O7
RDY/BUSY
NC
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
Ready/Busy Output
No Connect
Don’t Connect
TSOP
Top View
OE
A11
A9
A8
NC
WE
VCC
RDY/BUSY (or NC)
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
PDIP, SOIC
Top View
RDY/BUSY (or NC)
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
LCC, PLCC
Top View
A7
A12
RDY/BUSY (or NC)
DC
VCC
WE
NC
I/O1
I/O2
VSS
DC
I/O3
I/O4
I/O5
14
15
16
17
18
19
20
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
Rev. 0001H–12/99
Note: PLCC package pins 1 and 17 are
DON’T CONNECT.
1
The AT28C64 is accessed like a Static RAM for the read or
write cycles without the need for external components. Dur-
ing a byte write, the address and data are latched inter-
nally, freeing the microprocessor address and data bus for
other operations. Following the initiation of a write cycle,
the device will go to a busy state and automatically clear
and write the latched data using an internal control timer.
The device includes two methods for detecting the end of a
write cycle, level detection of RDY/BUSY (unless pin 1 is
N.C.) and DATA Polling of I/O
7
. Once the end of a write
cycle has been detected, a new access for a read or write
can begin.
The CMOS technology offers fast access times of 120 ns at
low power dissipation. When the chip is deselected the
standby current is less than 100 µA.
Atmel’s AT28C64 has additional features to ensure high
quality and manufacturability. The device utilizes error cor-
rection internally for extended endurance and for improved
data retention characteristics. An extra 32 bytes of
EEPROM are available for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
2
AT28C64(X)
AT28C64(X)
Device Operation
READ:
The AT28C64 is accessed like a Static RAM.
When CE and OE are low and WE is high, the data stored
at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in a high
impedance state whenever CE or OE is high. This dual line
control gives designers increased flexibility in preventing
bus contention.
BYTE WRITE:
Writing data into the AT28C64 is similar to
writing into a Static RAM. A low pulse on the WE or CE
input with OE high and CE or WE low (respectively) ini-
tiates a byte write. The address location is latched on the
falling edge of WE (or CE); the new data is latched on the
rising edge. Internally, the device performs a self-clear
before write. Once a byte write has been started, it will
automatically time itself to completion. Once a program-
ming operation has been initiated and for the duration of
t
WC
, a read operation will effectively be a polling operation.
FAST BYTE WRITE:
The AT28C64E offers a byte write
time of 200 µs maximum. This feature allows the entire
device to be rewritten in 1.6 seconds.
READY/BUSY:
Pin 1 is an open drain RDY/BUSY output
that can be used to detect the end of a write cycle.
RDY/BUSY is actively pulled low during the write cycle and
is released at the completion of the write. The open drain
connection allows for OR-tying of several devices to the
same RDY/BUSY line. The RDY/BUSY pin is not con-
nected for the AT28C64X.
DATA POLLING:
The AT28C64 provides DATA Polling to
signal the completion of a write cycle. During a write cycle,
an attempted read of the data being written results in the
complement of that data for I/O
7
(the other outputs are
indeterminate). When the write cycle is finished, true data
appears on all outputs.
WRITE PROTECTION:
Inadvertent writes to the device
are protected against in the following ways: (a) V
CC
sense –
if V
CC
is below 3.8V (typical) the write function is inhibited;
(b) V
CC
power on delay – once V
CC
has reached 3.8V the
device will automatically time out 5 ms (typical) before
allowing a byte write; and (c) write inhibit – holding any one
of OE low, CE high or WE high inhibits byte write cycles.
CHIP CLEAR:
The contents of the entire memory of the
AT28C64 may be set to the high state by the CHIP CLEAR
operation. By setting CE low and OE to 12 volts, the chip is
cleared when a 10 msec low pulse is applied to WE.
D E V I C E I DE NT I FI C A TI O N :
A n e x t r a 3 2 b y t e s o f
EEPROM memory are available to the user for device iden-
tification. By raising A9 to 12
±
0.5V and using address
locations 1FE0H to 1FFFH the additional bytes may be
written to or read from in the same manner as the regular
memory array.
3
DC and AC Operating Range
AT28C64-12
Operating
Temperature (Case)
V
CC
Power Supply
Com.
Ind.
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT28C64-15
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT28C64-20
0°C - 70°C
-40°C - 85°C
5V
±
10%
AT28C64-25
0°C - 70°C
-40°C - 85°C
5V
±
10%
Operating Modes
Mode
Read
Write
(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Chip Erase
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC programming waveforms.
3. V
H
= 12.0V
±
0.5V.
CE
V
IL
V
IL
V
IH
X
X
X
V
IL
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
V
H(3)
WE
V
IH
V
IL
X
V
IH
X
X
V
IL
High Z
High Z
I/O
D
OUT
D
IN
High Z
DC Characteristics
Symbol
I
LI
I
LO
I
SB1
I
SB2
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
Condition
V
IN
= 0V to V
CC
+ 1V
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
+ 1.0V
Com.
CE = 2.0V to V
CC
+ 1.0V
f = 5 MHz; I
OUT
= 0 mA
CE = V
IL
Ind.
Com.
Ind.
Min
Max
10
10
100
2
3
30
45
0.8
2.0
I
OL
= 2.1 mA
= 4.0 mA for RDY/BUSY
I
OH
= -400 µA
2.4
0.45
Units
µA
µA
µA
mA
mA
mA
mA
V
V
V
V
I
CC
V
IL
V
IH
V
OL
V
OH
V
CC
Active Current AC
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
4
AT28C64(X)
AT28C64(X)
AC Read Characteristics
AT28C64-12
Symbol
t
ACC
t
CE(1)
t
OE(2)
t
DF(3)(4)
t
OH
Parameter
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE High to Output Float
Output Hold from OE, CE or
Address, whichever occurred first
10
0
0
Min
Max
120
120
60
45
10
0
0
AT28C64-15
Min
Max
150
150
70
50
10
0
0
AT28C64-20
Min
Max
200
200
80
55
10
0
0
AT28C64-25
Min
Max
250
250
100
60
Units
ns
ns
ns
ns
ns
AC Read Waveforms
(1)(2)(3)(4)
Notes:
1. CE may be delayed up to t
ACC
- t
CE
after the address transition without impact on t
ACC
.
2. OE may be delayed up to t
CE
- t
OE
after the falling edge of CE without impact on t
CE
or by t
ACC
- t
OE
after an address change
without impact on t
ACC
.
3. t
DF
is specified from OE or CE whichever occurs first (C
L
= 5 pF).
4. This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
t
R
, t
F
< 20 ns
Pin Capacitance
f = 1 MHz, T = 25°C
(1)
Symbol
C
IN
C
OUT
Note:
Typ
4
8
Max
6
12
Units
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
1. This parameter is characterized and is not 100% tested.
5
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