MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by:
DSP56304/D
DSP56304
Advance Information
24-BIT DIGITAL SIGNAL PROCESSOR
Motorola designed the ROM-based DSP56304 to support multifunction wireless and
embedded DSP applications. In addition to the large on-chip ROM spaces, the DSP56304 also
has a ROM patch feature that facilitates updates to the on-chip mask Program ROM-based
on-chip software. The DSP56304 includes a triple timer module, Host Interface (HI08), an
Enhanced Synchronous Serial Interface (ESSI), and a Serial Communications Interface (SCI).
The DSP56300 core family includes a Phase Lock Loop (PLL), External Memory Interface
(EMI), Data Arithmetic Logic Unit (Data ALU), 24-bit addressing, instruction cache, and
DMA. The DSP56304 offers 66/80 MIPS using an internal 66/80 MHz clock at 3.0–3.6 volts.
16
6
6
3
Memory Expansion Area
Triple
Timer
Host
Interface
HI08
ESSI
Interface
SCI
Interface
Program RAM
1024
×
24*
Program ROM
33792
×
24
*default
PIO_EB
PM_EB
Y Data
X Data
RAM
RAM
1792
×
24*
3328
×
24*
ROM
ROM
9216
×
24
9216
×
24
*default
*default
XM_EB
YM_EB
Peripheral
Expansion Area
Address
Generation
Unit
Six Channel
DMA Unit
Boot-
strap
ROM
YAB
XAB
PAB
DAB
External
Address
Bus
Switch
External
Bus
Interface
&
I-Cache
Control
18
Address
24-Bit
DSP56300
Core
DDB
YDB
13
Control
Internal
Data
Bus
Switch
EXTAL
XTAL
Clock
Generator
PLL
2
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
XDB
PDB
GDB
External
Data Bus
Switch
24
Data
Data ALU
24
×
24 + 56
→
56-bit MAC JTAG
Two 56-bit Accumulators
OnCE™
56-bit Barrel Shifter
Power
Mngmnt
5
DE
AA0853
Figure 1
DSP56304 Block Diagram
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Preliminary Data
©1996 MOTOROLA, INC.
TABLE OF CONTENTS
SECTION 1
SECTION 2
SECTION 3
SECTION 4
SECTION 5
APPENDIX A
SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
POWER CONSUMPTION BENCHMARK . . . . . . . . . . . . . . . . . . A-1
INDEX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Index-1
FOR TECHNICAL ASSISTANCE:
Telephone:
Email:
Internet:
1-800-521-6274
dsphelp@dsp.sps.mot.com
http://www.motorola-dsp.com
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
“deasserted”
Examples:
Used to indicate a signal that is active when pulled low (For example, the RESET
pin is active when low.)
Means that a high true (active high) signal is high or that a low true (active low)
signal is low
Means that a high true (active high) signal is low or that a low true (active low)
signal is high
Signal/Symbol
PIN
PIN
PIN
PIN
Note:
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
Preliminary Data
ii
DSP56304/D
MOTOROLA
DSP56304
Features
FEATURES
DSP56304 FEATURES
High Performance DSP56300 Core
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
66/80 Million Instructions Per Second (MIPS) with a 66/80 MHz clock
Object code compatible with the DSP56000 core
Highly parallel instruction set
Fully pipelined 24
×
24-bit parallel Multiplier-Accumulator (MAC)
56-bit parallel barrel shifter
24-bit or 16-bit arithmetic support under software control
Position independent code support
Addressing modes optimized for DSP applications
On-chip instruction cache controller
On-chip memory-expandable hardware stack
Nested hardware DO loops
Fast auto-return interrupts
On-chip concurrent six-channel DMA controller
On-chip Phase Lock Loop (PLL) and clock generator
On-Chip Emulation (OnCE™) module
JTAG Test Access Port (TAP)
Address Tracing mode reflects internal accesses at the external port
Preliminary Data
MOTOROLA
DSP56304/D
iii
DSP56304
DSP56304 Features
On-chip Memories
•
Program RAM, Instruction Cache, X data RAM, and Y data RAM size is
programmable:
Switch
Mode
disabled
disabled
enabled
enabled
Program
RAM Size
1024
×
24-bit
0
3584
×
24-bit
2560
×
24-bit
Instruction
Cache Size
0
1024
×
24-bit
0
1024
×
24-bit
X Data RAM
Size
3328
×
24-bit
3328
×
24-bit
2048
×
24-bit
2048
×
24-bit
Y Data RAM
Size
1792
×
24-bit
1792
×
24-bit
512
×
24-bit
512
×
24-bit
Instruction
Cache
disabled
enabled
disabled
enabled
•
•
•
33, 792
×
24-bit Program ROM with Patch mode update capability using
instruction cache memory space
9,216
×
24-bit X data ROM and 9,216
×
24-bit Y data ROM
192
×
24-bit bootstrap ROM
Off-chip Memory Expansion
•
Data memory expansion to two 256 K
×
24-bit word memory spaces (the
usage of address attribute pins and/or DRAM interface may further
extend the data memory expansion up to two 16 M
×
24-bit words
memory space)
Program memory expansion to one 256 K
×
24-bit word memory space
(the usage of address attribute pins and/or DRAM interface may further
extend the program memory expansion up to two 16 M
×
24-bit words
memory space)
External memory expansion port
Chip select logic requires no additional circuitry to interface to SRAMs
and SSRAMs
On-chip DRAM controller requires no additional circuitry to interface to
DRAMs
•
•
•
•
Preliminary Data
iv
DSP56304/D
MOTOROLA
DSP56304
Target Applications
On-chip Peripherals
•
8-bit parallel Host Interface (HI08), ISA-compatible bus interface,
providing a cost-effective solution for applications not requiring the PCI
bus
Two Enhanced Synchronous Serial Interfaces (ESSI0 and ESSI1)
Serial Communications Interface (SCI) with baud rate generator
Triple timer module
Up to thirty-four programmable General Purpose I/O pins (GPIO),
depending on which peripherals are enabled
•
•
•
•
Reduced Power Dissipation
•
•
•
•
Very low power CMOS design
Wait and Stop low power standby modes
Fully-static logic, operation frequency down to DC
Optimized power management circuitry
TARGET APPLICATIONS
The DSP56304 is intended for use in embedded multifunction DSP applications
requiring large on-board ROM spaces, such as wireless products that combine
standard cellular phone operation with options such as two-way digital paging
and fax capability in one unit.
Preliminary Data
MOTOROLA
DSP56304/D
v
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