kHz Range Crystal Devices
Digital Temperature Compensated Crystal Oscillator
Surface Mount Type DTCXO KT3225T Series
CMOS/ 3.0V Typ./ 3.2×2.5mm
Features
• Miniature SMD type (3.2×2.5×1.0mm)
• Built-in 32.768kHz D-TCXO
• High frequency stability :
±5.0x10
-
6
/
-40
to
+85°C
• Low supply current : 1.5μA typ (V
DD
=3.0V)
• Temperature compensated voltage
Range : 2.0V to 5.5V
How to Order
KT3225T 32768 E A W 30 T xx
①
②
③ ④ ⑤ ⑥ ⑦ ⑧
O
①
Series
②
utput Frequency
③
Frequency Stability
④
Lower Temperature
A
No Temp. Compensated
±3.8×10
-
6
D
±5.0×10
-
6
E
A
C
E
30
33
50
-40°C
-30°C
-20°C
3.0V
3.3V
5.0V
Applications
• High accuracy time references
• Microcontroller with built in RTC
⑤
Upper Temperature
W
T
R
+85°C
+70°C
+60°C
⑥
Supply Voltage
RoHS Compliant
⑦
Initial Frequency
Tolerance
A
5±5×10
-
6
B
0±5×10
-
6
T
TCXO
⑧
Option Code
Specifications
Item
Nominal Frequency
Oscillation Output Voltage
Temperature Compensated Voltage
Storage Temperature
Operating Temperature
Frequency Tolerance
Frequency Stability vs Temp.
Frequency Stability vs Supply Voltage
Frequency Aging
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
DUTY Ratio
Rise Time
Fall Time
Start-up Time
Power Supply Current1
Power Supply Current2
Output Load Condition
Symbol
f_
nom
V
DD
V
TEM
T_
stg
T_
use
―
fo-Tc
df/ fo
f
_age
V
OL
V
OH
V
IL
V
IH
Duty
tr
tf
Conditions
Packaging (Tape & Reel 3000pcs/ reel)
Specifications
Min.
―
1.3
2.0
-40
-40
-3.0
-5.0
-1.0
-3.0
0.0
2.2
0.0
0.8×V
DD
40
―
―
―
―
―
―
―
Typ.
32.768
3.0
3.0
+25
+25
―
―
―
―
―
―
―
―
―
―
―
―
―
0.6
1.5
―
Max.
―
5.5
5.5
+85
+85
+3.0
+5.0
+1.0
+3.0
0.8
3.0
0.2×V
DD
5.5
60
100
100
1.0
3.0
2.0
4.0
15.0
Units
kHz
V
V
°C
°C
×10
-
6
×10
-
6
×10
-
6
/ V
×10
-
6
V
V
V
V
%
nsec
nsec
sec
sec
μA
μA
pF
(Unit: mm)
Ta=25±2°C
E : Ta=-40 to
+85°C
V
DD
=2.0
to 5.5V, Ta=25±2°C
I
OL
=+1.0mA,
V
DD
=3V
I
OH
=-1.0mA,
V
DD
=3V
CL=15pF
20%V
DD
→80%V
DD
, CL=15pF, V
DD
=3V
80%V
DD
→20%V
DD
, CL=15pF, V
DD
=3V
Ta=25°C
t_
str
Ta=-40 to 85°C
I
CC
1
CLKOE=V
SS
I
CC
2
CLKOE=V
DD
L_CMOS CMOS Output
(Unit: mm)
Dimensions
3.2±0.2
#8
#7
#6
#5
Recommended Land Pattern
0.55
0.6
0.6
0.55
2.5±0.2
K
#1
#2
#3
#4
1.0 max.
C0.15
#1
#2
#3
#4
Pin No
#1
#2
#3
#4
#5
#6
#7
#8
Function
CLKOE
N.C
N.C
V
SS
CLKOUT
N.C
N.C
V
DD
1.1
0.85
0.45
0.5
0.27
1.1
0.85
0.4
0.4
0.4
0.35
0.7
#8
0.4
#7
0.5
#6
0.5
#5
R0.15
Note: A capacitor of value 0.01µF between V
DD
and GND is recommended.
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
