MC68HC11A0CP2 datasheet, PDF - EEWORLD Datasheet

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MC68HC11A0CP2: Description8-BIT, MROM, 2MHz, MICROCONTROLLER, PDIP48, PLASTIC, DIP-48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size4MB，158 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MC68HC11A0CP2 Overview

8-BIT, MROM, 2MHz, MICROCONTROLLER, PDIP48, PLASTIC, DIP-48

MC68HC11A0CP2 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	NXP
Parts packaging code	DIP
package instruction	PLASTIC, DIP-48
Contacts	48
Reach Compliance Code	compliant
Has ADC	YES
Address bus width	16
bit size	8
CPU series	6800
maximum clock frequency	8 MHz
DAC channel	NO
DMA channel	NO
External data bus width	8
JESD-30 code	R-PDIP-T48
JESD-609 code	e0
length	61.72 mm
Number of I/O lines	34
Number of terminals	48
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
PWM channel	NO
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP48,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (bytes)	256
rom(word)	0
ROM programmability	MROM
Maximum seat height	5.08 mm
speed	2 MHz
Maximum slew rate	35 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	HCMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER

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Freescale Semiconductor, Inc.

MC68HC11A8

HCMOS Single-Chip Microcontroller

Freescale Semiconductor, Inc...

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Freescale Semiconductor, Inc.

TABLE OF CONTENTS

Paragraph

Number

Title

1 INTRODUCTION

1.1

1.1.1

1.1.2

1.2

1.3

1.4

Features .................................................................................................... 1-1

Hardware Features ............................................................................ 1-1

Software Features ............................................................................. 1-1

General Description ................................................................................... 1-1

Programmer’s Model ................................................................................. 1-2

Summary of M68HC11 Family .................................................................. 1-3

2 SIGNAL DESCRIPTIONS AND OPERATING MODES

Page

Number

Freescale Semiconductor, Inc...

2.1

Signal Pin Descriptions ............................................................................. 2-1

2.1.1

Input Power (V

) and Ground (V

) ................................................ 2-1

2.1.2

Reset (RESET) .................................................................................. 2-1

2.1.3

Crystal Driver and External Clock Input (XTAL, EXTAL) ................... 2-1

2.1.4

E Clock Output (E) ............................................................................ 2-3

2.1.5

Interrupt Request (IRQ) ..................................................................... 2-3

2.1.6

Non-Maskable Interrupt (XIRQ) ......................................................... 2-3

2.1.7

Mode A/Load Instruction Register and Mode B/Standby Voltage (MODA/

LIR, MODB/V

STBY

) 2-3

2.1.8

A/D Converter Reference Voltages (V

, V

) ................................. 2-4

2.1.9

Strobe B and Read/Write (STRB/R/W) ............................................. 2-4

2.1.10

Strobe A and Address Strobe (STRA/AS) ......................................... 2-4

2.1.11

Port Signals ....................................................................................... 2-4

2.1.11.1

Port A ........................................................................................ 2-5

2.1.11.2

Port B ........................................................................................ 2-5

2.1.11.3

Port C ........................................................................................ 2-5

2.1.11.4

Port D ........................................................................................ 2-5

2.1.11.5

Port E ........................................................................................ 2-6

2.2

Operating Modes ....................................................................................... 2-6

2.2.1

Single-Chip Operating Mode ............................................................. 2-6

2.2.2

Expanded Multiplexed Operating Mode ............................................ 2-6

2.2.3

Special Bootstrap Operating Mode ................................................... 2-8

2.2.4

Additional Boot Loader Program Options ........................................ 2-10

2.2.5

Special Test Operating Mode .......................................................... 2-10

3 ON-CHIP MEMORY

3.1

3.2

3.3

3.4

3.5

3.5.1

Memory Maps ............................................................................................ 3-1

RAM and I/O Mapping Register (INIT) ...................................................... 3-4

ROM .......................................................................................................... 3-5

RAM .......................................................................................................... 3-5

EEPROM ................................................................................................... 3-5

EEPROM Programming Control Register (PPROG) ......................... 3-6

iii

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3.5.2

3.5.2.1

3.5.2.2

3.5.2.3

3.5.2.4

3.5.2.5

3.5.3

3.5.3.1

3.5.3.2

Programming/Erasing Internal EEPROM .......................................... 3-7

Read .......................................................................................... 3-7

Programming ............................................................................. 3-7

Bulk Erase ................................................................................. 3-8

Row Erase ................................................................................. 3-8

Byte Erase ................................................................................. 3-9

System Configuration Register (CONFIG) ........................................ 3-9

Programming and Erasure of the CONFIG Register ............... 3-10

Operation of the Configuration Mechanism ............................. 3-12

4 PARALLEL I/O

4.1

4.2

4.3

4.3.1

4.3.2

4.4

4.4.1

4.4.2

4.5

General-Purpose I/O (Ports C and D) ....................................................... 4-1

Fixed Direction I/O (Ports A, B, and E) ...................................................... 4-1

Simple Strobed I/O .................................................................................... 4-2

Strobed Input Port C .......................................................................... 4-2

Strobed Output Port B ....................................................................... 4-2

Full Handshake I/O .................................................................................... 4-2

Input Handshake Protocol ................................................................. 4-3

Output Handshake Protocol .............................................................. 4-3

Parallel I/O Control Register (PIOC) ......................................................... 4-4

5 SERIAL COMMUNICATIONS INTERFACE

5.1

5.1.1

5.1.2

5.1.3

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.8.1

5.8.2

5.8.3

5.8.4

5.8.5

Overview and Features ............................................................................. 5-1

SCI Two-Wire System Features ........................................................ 5-1

SCI Receiver Features ...................................................................... 5-1

SCI Transmitter Features .................................................................. 5-1

Data Format .............................................................................................. 5-1

Wake-Up Feature ...................................................................................... 5-2

Receive Data (RxD) .................................................................................. 5-2

Start Bit Detection ..................................................................................... 5-3

Transmit Data (TxD) .................................................................................. 5-5

Functional Description ............................................................................... 5-5

SCI Registers ............................................................................................ 5-5

Serial Communications Data Register (SCDR) ................................. 5-6

Serial Communications Control Register 1 (SCCR1) ........................ 5-8

Serial Communications Control Register 2 (SCCR2) ........................ 5-8

Serial Communications Status Register (SCSR) ............................ 5-10

Baud Rate Register (BAUD) ............................................................ 5-11

6 SERIAL PERIPHERAL INTERFACE

6.1

6.2

6.2.1

6.2.2

6.2.3

Overview and Features ............................................................................. 6-1

SPI Signal Descriptions ............................................................................. 6-1

Master In Slave Out (MISO) .............................................................. 6-1

Master Out Slave In (MOSI) .............................................................. 6-1

Serial Clock (SCK) ............................................................................ 6-2

MC68HC11A8

TECHNICAL DATA

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6.2.4

6.3

6.4

6.4.1

6.4.2

6.4.3

Slave Select (SS) .............................................................................. 6-2

Functional Description ............................................................................... 6-3

SPI Registers ............................................................................................ 6-4

Serial Peripheral Control Register (SPCR) ....................................... 6-4

Serial Peripheral Status Register (SPSR) ......................................... 6-5

Serial Peripheral Data l/O Register (SPDR) ...................................... 6-6

7 ANALOG-TO-DIGITAL CONVERTER

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

Conversion Process .................................................................................. 7-1

Channel Assignments ............................................................................... 7-1

Single-Channel Operation ......................................................................... 7-2

Multiple-Channel Operation ....................................................................... 7-2

Operation in STOP and WAIT Modes ....................................................... 7-3

A/D Control/Status Register (ADCTL) ....................................................... 7-3

A/D Result Registers 1, 2, 3, and 4 (ADR1, ADR2, ADR3, and ADR4) .... 7-5

A/D Power-Up and Clock Select ............................................................... 7-5

8 PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR

8.1

Programmable Timer ................................................................................. 8-1

8.1.1

Counter .............................................................................................. 8-1

8.1.2

Input Capture ..................................................................................... 8-1

8.1.3

Output Compare ................................................................................ 8-2

8.1.4

Output Compare 1 I/O Pin Control .................................................... 8-2

8.1.5

Timer Compare Force Register (CFORC) ......................................... 8-3

8.1.6

Output Compare 1 Mask Register (OC1M) ....................................... 8-3

8.1.7

Output Compare 1 Data Register (OC1D) ........................................ 8-4

8.1.8

Timer Control Register 1 (TCTL1) ..................................................... 8-4

8.1.9

Timer Control Register 2 (TCTL2) ..................................................... 8-5

8.1.10

Timer Interrupt Mask Register 1 (TMSK1) ........................................ 8-5

8.1.11

Timer Interrupt Flag Register 1 (TFLG1) ........................................... 8-5

8.1.12

Timer Interrupt Mask Register 2 (TMSK2) ........................................ 8-6

8.1.13

Timer Interrupt Flag Register 2 (TFLG2) ........................................... 8-7

8.2

Real-Time Interrupt ................................................................................... 8-8

8.3

Pulse Accumulator .................................................................................... 8-8

8.3.1

Pulse Accumulator Control Register (PACTL) .................................. 8-8

9 RESETS, INTERRUPTS, AND LOW POWER MODES

9.1

Resets ....................................................................................................... 9-1

9.1.1

External RESET Pin .......................................................................... 9-1

9.1.2

Power-On Reset ................................................................................ 9-1

9.1.2.1

CPU ........................................................................................... 9-2

9.1.2.2

Memory Map ............................................................................. 9-3

9.1.2.3

Parallel l/O ................................................................................. 9-3

9.1.2.4

Timer ......................................................................................... 9-3

9.1.2.5

Real-Time Interrupt ................................................................... 9-4

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