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MT5VDDT872HIY-265XX

Description
DDR DRAM Module, 8MX72, 0.75ns, CMOS, LEAD FREE, SODIMM-200
Categorystorage    storage   
File Size831KB,39 Pages
ManufacturerMicron Technology
Websitehttp://www.mdtic.com.tw/
Environmental Compliance
Download Datasheet Parametric View All

MT5VDDT872HIY-265XX Overview

DDR DRAM Module, 8MX72, 0.75ns, CMOS, LEAD FREE, SODIMM-200

MT5VDDT872HIY-265XX Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerMicron Technology
Parts packaging codeSODIMM
package instructionDIMM,
Contacts200
Reach Compliance Codecompliant
ECCN codeEAR99
access modeSINGLE BANK PAGE BURST
Maximum access time0.75 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeR-XZMA-N200
JESD-609 codee4
memory density603979776 bit
Memory IC TypeDDR DRAM MODULE
memory width72
Number of functions1
Number of ports1
Number of terminals200
word count8388608 words
character code8000000
Operating modeSYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize8MX72
Package body materialUNSPECIFIED
encapsulated codeDIMM
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)260
Certification statusNot Qualified
self refreshYES
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.3 V
Nominal supply voltage (Vsup)2.5 V
surface mountNO
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceGold (Au)
Terminal formNO LEAD
Terminal locationZIG-ZAG
Maximum time at peak reflow temperature30
64MB, 128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
Features
DDR SDRAM Small-Outline DIMM
MT5VDDT872H(I) – 64MB
MT5VDDT1672H(I) – 128MB
MT5VDDT3272H(I) – 256MB
For the latest data sheet, please refer to the Micron
®
Web site:
www.micron.com/products/modules
Features
• 200-pin, small-outline dual in-line memory module
(DDR SODIMM)
• Fast data transfer rates: PC2100, or PC2700
• Utilizes 266 MT/s and 333 MT/s DDR SDRAM
components
• 64MB (8 Meg x 72), 128MB (16 Meg x 72), and
256MB (128 Meg x 32)
• Supports ECC error detection and correction
• V
DD
= V
DD
Q= +2.5V
• V
DDSPD
= +2.3V to +3.6V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Selectable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes 15.625µs
(64MB); 7.8125µs (128MB, 256MB) maximum
average periodic refresh interval
• Serial Presence Detect (SPD) with EEPROM
• Selectable READ CAS latency for maximum
compatibility
• Gold edge contacts
Figure 1:
200-Pin SODIMM (MO-224)
64MB
1.25in. (31.75mm)
128MB, 256MB 1.25in. (31.75mm)
Options
Marking
• Operating temperature
Commercial (0°C
T
A
+70°C)
None
Industrial (-40°C
T
A
+85°C)
I
• Package
200-pin SODIMM (standard)
G
1
200-pin SODIMM (lead-free)
Y
2
• Memory clock, frequency, CAS latency
6ns (167 MHz), 333 MT/s, CL = 2.5
-335
7.5ns (133 MHz), 266 MT/s, CL = 2
-262
1
7.5ns (133 MHz), 266 MT/s, CL = 2
-26A
1
7.5ns (133 MHz), 266 MT/s, CL = 2.5
-265
1
• PCB Height
1.25in. (31.75mm)
Notes: 1. Consult factory for product availability.
Shown for legacy products and backwards
compatibility; not recommended for new
designs.
2. CL = Device CAS (READ) latency.
pdf: 09005aef80a8e793, source: 09005aef80a8e767
DD5C8_16_32x72H_1.fm - Rev. E 8/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

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