MPC8567VTAQJJA datasheet, PDF - EEWORLD Datasheet

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MPC8567VTAQJJA: Description32-BIT, 1000 MHz, RISC PROCESSOR, PBGA1023; Categorysemiconductor The embedded processor and controller; File Size1MB，139 Pages; ManufacturerFREESCALE (NXP)

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MPC8567VTAQJJA Overview

32-BIT, 1000 MHz, RISC PROCESSOR, PBGA1023

MPC8567VTAQJJA Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	1023
Maximum supply/operating voltage	1.16 V
Minimum supply/operating voltage	1.04 V
Rated supply voltage	1.1 V
External data bus width	0.0
Line speed	1000 MHz
Processing package description	33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCBGA-1023
state	ACTIVE
packaging shape	SQUARE
Package Size	GRID ARRAY
surface mount	Yes
Terminal form	BALL
Terminal spacing	1 mm
terminal coating	TIN SILVER
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Address bus width	0.0
Number of digits	32
boundary scan	Yes
Maximum FCLK clock frequency	166 MHz
floating point unit	Yes
Integrated cache	Yes
low power mode	Yes
Microprocessor type	RISC PROCESSOR

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Freescale Semiconductor

Technical Data

Document Number: MPC8568EEC

Rev. 1, 10/2010

MPC8568E/MPC8567E

PowerQUICC III

Integrated Processor

Hardware Specifications

Due to feature similarities, this document covers both the

MPC8568E and MPC8567E features. For simplicity,

MPC8568 may only be mentioned throughout the document.

The MPC8567E feature differences are as follows:

• The MPC8567E PCI-Express supports x1/x2/x4, but

does not have x8 support.

• Does not have eTSEC1, eTSEC2, or TLU

Note that both the MPC8568E and MPC8567E have their

own pin assignment tables.

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Contents

MPC8568E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 10

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Ethernet Interface and MII Management . . . . . . . . . . 26

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . 61

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

HDLC, BISYNC, Transparent and

Synchronous UART . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

System Design Information . . . . . . . . . . . . . . . . . . . 130

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 136

Document Revision History . . . . . . . . . . . . . . . . . . 138

MPC8568E Overview

— Byte-accessible ECC uses read-modify-write transaction accesses for smaller-than-cache-line

accesses.

1.2.2

e500 Coherency Module (ECM) and Address Map

The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus

between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable

memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be

routed or dispatched to target modules on the device.

The MPC8568E supports a flexible 36-bit physical address map. Conceptually, the address map consists of

local space and external address space. The local address map is supported by eight local access windows

that define mapping within the local 36-bit (64-Gbyte) address space.

The MPC8568E can be made part of a larger system address space through the mapping of translation

windows. This functionality is included in the address translation and mapping units (ATMUs). Both

inbound and outbound translation windows are provided. The ATMUs allows the MPC8568E to be part of

larger address maps such as the PCI or PCI Express 64-bit address environment and the RapidIO

environment.

1.2.3

•

QUICC Engine

Integrated 8-port L2 Ethernet switch

— 8 connection ports of 10/100 Mbps MII/RMII & one CPU internal port

— Each port supports four priority levels

— Priority levels used with VLAN tags or IP TOS field to implement QoS

— QoS types of traffic, such as voice, video, and data

Includes support for the following protocols:

— ATM SAR up to 622 Mbps (OC-12) full duplex, with ATM traffic shaping (ATF TM4.1) for

up to 64K ATM connections

— ATM AAL1 structured and unstructured Circuit Emulation Service (CES 2.0)

— IMA and ATM Transmission convergence sub-layer

— ATM OAM handling features compatible with ITU-T I.610

— PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the

following RFCs: 1661, 1662, 1990, 2686 and 3153

— IP termination support for IPv4 and IPv6 packets including TOS, TTL and header checksum

processing

— ATM (AAL2/AAL5) to Ethernet (IP) interworking

— Extensive support for ATM statistics and Ethernet RMON/MIB statistics.

— 256 channels of HDLC/Transparent or 128 channels of SS#7

Includes support for the following serial interfaces:

— Two UL2/POS-PHY interfaces with 124 Multi-PHY addresses on UTOPIA interface each or

31 Multi-PHY addresses on the POS interface each.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

•

Freescale Semiconductor

MPC8568E Overview

— Three 1-Gbps Ethernet interfaces using three GMII, two RGMII/TBI/RTBI

— Up to eight 10/100-Mbps Ethernet interfaces using MII or RMII

— Up to eight T1/E1/J1/E3 or DS-3 serial interfaces

1.2.4

Integrated Security Engine (SEC)

The SEC is a modular and scalable security core optimized to process all the algorithms associated with

IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is

designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of

the data. The version of the SEC used in the MPC8568E is specifically capable of performing single-pass

security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i.

• Optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and

3GPP

• Compatible with code written for the Freescale MPC8541E and MPC8555E devices

• XOR engine for parity checking in RAID storage applications.

• Four crypto-channels, each supporting multi-command descriptor chains

• Cryptographic execution units:

— PKEU—public key execution unit

— DEU—Data Encryption Standard execution unit

— AESU—Advanced Encryption Standard unit

— AFEU—ARC four execution unit

— MDEU—message digest execution unit

— KEU—Kasumi execution unit

— RNG—Random number generator

1.2.5

Enhanced Three-Speed Ethernet Controllers

The MPC8568E has two on-chip enhanced three-speed Ethernet controllers (eTSECs). The eTSECs

incorporate a media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps

Ethernet/802.3 networks with MII, RMII, GMII, RGMII, TBI, and RTBI physical interfaces. The eTSECs

include 2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions.

The MPC8568E eTSECs support programmable CRC generation and checking, RMON statistics, and

jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache

to speed classification or other frame processing. They are IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x,

IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab-compatible.

The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models.

Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with

minimal change.

Some of the key features of these controllers include:

• Flexible configuration for multiple PHY interface configurations.

Table 1

lists available

configurations.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

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