IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
FEATURES:
–
–
–
–
–
–
–
–
–
Typical
t
SK(0)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
Extended commercial range of -40°C to +85°C
V
CC
= 3.3V ±0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4µ W typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
IDT74LVC16952A
DESCRIPTION:
This 16-bit registered transceiver is built using advanced dual metal
CMOS technology. This high-speed, low power device is organized as two
independent 8-bit D-type registered transceivers with separate input and
output control for independent control of data flow in either direction. For
example, the A-to-B Enable (CEAB) must be LOW to enter data from the A
port. CLKAB controls the clocking function. When CLKAB toggles from LOW-
to-HIGH, the data present on the A port will be clocked into the register.
OEAB
performs the output enable function on the B port. Data flow from the
B port to A port is similar but requires using
CEBA,
CLKBA, and
OEBA
inputs.
Full 16-bit operation is achieved by tying the control pins of the independent
transceivers together.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC16952A has been designed with a
±
24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance
Drive Features for LVC16952A:
– High Output Drivers: ±24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
54
1
CEBA
1
CLKBA
1
OEAB
3
1
CEAB
1
CLKAB
2
2
CEAB
2
CLKAB
27
55
1
2
OEAB
26
2
CEBA
2
CLKBA
30
28
31
1
OEBA
56
29
2
OEBA
C
1
A
1
5
CE
D
C
CE
D
52
2
A
1
1
B
1
15
C
CE
D
C
CE
D
42
2
B
1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1998 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4492/1
IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OEAB
1
CLK AB
1
CEAB
ABSOLUTE MAXIMUM RATINGS
56
55
54
53
52
51
50
49
48
47
46
45
1
OEBA
1
CLKBA
1
CEBA
(1)
Unit
V
°C
mA
mA
mA
LVC Link
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through
each V
CC
or GND
Max.
– 0.5 to +6.5
– 65 to +150
– 50 to +50
– 50
±100
GND
1
A
1
1
A
2
GND
1
B
1
1
B
2
V
CC
1
A
3
1
A
4
1
A
5
V
CC
1
B
3
1
B
4
1
B
5
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
44
SO56-1
SO56-2 43
SO56-3
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output
Capacitance
I/O Port
Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
LVC Link
GND
2
A
4
2
A
5
2
A
6
GND
2
B
4
2
B
5
2
B
6
V
CC
2
A
7
2
A
8
V
CC
2
B
7
2
B
8
NOTE:
1. As applicable to the device type.
GND
2
CEAB
2
CLKAB
2
OEAB
GND
2
CEBA
2
CLKBA
2
OEBA
FUNCTION TABLE
xCEAB
H
X
L
L
X
(1, 3)
xAx
X
X
L
H
X
Outputs
xBx
B
0(2)
B
0(2)
L
H
Z
Inputs
xCLKAB
xOEAB
X
L
L
↑
↑
X
L
L
L
H
SSOP/ TSSOP/ TVSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
xOEAB
xOEBA
xCEAB
xCEBA
xCLKAB
xCLKBA
xAx
xBx
Description
A-to-B Output Enable Inputs (Active LOW)
B-to-A Output Enable Inputs (Active LOW)
A-to-B Clock Enable Inputs (Active LOW)
B-to-A Clock Enable Inputs (Active LOW)
A-to-B Clock Inputs
B-to-A Clock Inputs
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑
= LOW-to-HIGH Transition
2. Output level of B before the indicated steady-state input conditions
were established
3. A-to-B data flow is shown; B-toA data flow is similar but uses, xCEBA,
xCLKBA, and xOEBA.
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40
O
C to +85
O
C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= – 18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
3.6
≤
V
IN
≤
5.5V
(2)
Quiescent Power Supply
Current Variation
One input at V
CC
- 0.6V
other inputs at V
CC
or GND
—
—
—
—
—
—
—
– 0.7
100
—
—
—
±50
– 1.2
—
10
10
500
µA
LVC Link
Test Conditions
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
V
O
= 0 to 5.5V
Min.
1.7
2
—
—
—
—
Typ.
(1)
—
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
±10
Unit
V
V
µA
µA
µA
V
mV
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
Test Conditions
(1)
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 6mA
I
OH
= – 12mA
Min.
V
CC
– 0.2
2
1.7
2.2
2.4
I
OH
= – 24mA
I
OL
= 0.1mA
I
OL
= 6mA
I
OL
= 12mA
V
CC
= 2.7V
V
CC
= 3.0V
I
OL
= 12mA
I
OL
= 24mA
2.2
—
—
—
—
—
Max.
—
—
—
—
—
—
0.2
0.4
0.7
0.4
0.55
LVC Link
Unit
V
V
CC
= 2.3V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3.0V
V
CC
= 3.0V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate V
CC
range. T
A
= – 40°C to +85°C.
3
IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V
±
0.3V, TA = 25°C
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per transceiver Outputs enabled
Power Dissipation Capacitance per transceiver Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
87
43
Unit
pF
pF
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SU
t
H
t
SU
t
H
t
W
t
SK
(o)
Parameter
Propagation Delay
xCLKAB, xCLKBA to xBx, xAx
Output Enable Time
xOEBA, xOEAB to xAx, xBx
Output Disable Time
xOEBA, xOEAB to xAx, xBx
Set-up Time, HIGH or LOW
xAx, xBx Before xCLKAB↑, xCLKBA↑
Hold Time, HIGH or LOW
xAx, xBx After xCLKAB↑, xCLKBA↑
Set-up Time, HIGH or LOW
xCEAB, xCEBA Before xCLKAB↑, xCLKBA↑
Hold Time, HIGH or LOW
xCEAB, xCEBA After xCLKAB↑, xCLKBA↑
Pulse Width HIGH or LOW
xCLKAB or xCLKBA
Output Skew
(2)
Min.
—
—
—
3.4
0.5
1.8
1.1
3.3
—
Max.
7.6
8
7.1
—
—
—
—
—
—
V
CC
= 3.3V±0.3V
Min.
1.6
1.1
1.9
2.8
0.5
1.4
1.9
3.3
—
Max.
6.6
6.6
6.7
—
—
—
—
—
500
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ps
NOTES:
1. See test circuits and waveforms. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC16952A
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
PROPAGATION DELAY
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC
(1)
= 3.3V ±0.3V
6
2.7
1.5
300
300
50
V
CC
(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC
(2)
= 2.5V ±0.2V Unit
2 x Vcc
V
Vcc
V
CC
/ 2
150
150
30
V
V
mV
mV
pF
LVC Link
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
Pulse
(1, 2)
Generator
V
IN
D.U.T.
500
Ω
C
L
V
OUT
V
LOAD
Open
GND
ENABLE AND DISABLE TIMES
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SW ITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SW ITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL+
V
LZ
V
OL
V
OH
V
OH-
V
HZ
0V
R
T
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
LVC Link
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
LVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
Switch
V
LOAD
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
LVC Link
t
SU
t
H
GND
Open
t
REM
OUTPUT SKEW - tsk (x)
V
IH
INPUT
V
T
0V
V
OH
OUTPUT 1
V
T
V
OL
V
OH
OUTPUT 2
t
PLH2
t
PHL2
V
T
V
OL
SYNCHRONOUS
CONTROL
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC Link
t
PLH1
t
PHL1
PULSE WIDTH
LOW -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
V
T
LVC Link
V
T
t
SK
(x)
t
SK
(x)
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
LVC
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
Link
5
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