Preliminary
Datasheet
R2J25953
H-Bridge Control High Speed Power Switching
with Built-in Driver IC and Power MOS FET
Description
The R2J25953 multi-chip module incorporates high-side Pch MOS FET, low-side Nch MOS FET, and Bi-CMOS driver
in a single HSOP-36 package.
R07DS0044EJ0300
Rev.3.00
Sep 01, 2010
Features
For Automotive application
Built-in low on state resistance MOS FET.
(Pch: 16 m Max., Nch: 11 m Max.)
Pch MOS FET is adopted on the high-side, and the charge pump noise was lost.
Built-in protection circuit of Thermal shut-down (TSD), Low Voltage Inhit (LVI), Overvoltage Detection (OVD)
and Overcurrent Detection.
Built-in diagnostic function.
Built-in cross-conduction protection.
Small Surface mounting package: HSOP-36
Block Diagram
Reverce battery
protection device
VBAT
Vz
Cp
M
VB1
VBS1
VCC
VBS2
VB2
Pch MOS
Pch MOS
Dr.
LVI, OVD
Overcurrent detection
Dr.
OUT1
TSD
OUT2
Dr.
Nch MOS
Logic
Dr.
Nch MOS
PGND1
PWM
INA
INB
DIAG
LGND
V30
C1
PGND2
Pull-up in the Microcomputer
R1 power supply
Microcomputer
R07DS0044EJ0300 Rev.3.00
Sep 01, 2010
Page 1 of 16
R2J25953
Preliminary
Outline
OUT1
NC
VBS1
GND
V30
GND
VBS2
VCC
NC
OUT2
NC
VB1
NC
VB2
19
36
TAB1
TAB3
TAB2
OUT1
1
18
NC
OUT1
PWM
INA
INB
GND
LGND
GND
DIAG
NC
OUT2
NC
Pin Description
Pin No.
1 to 3
4
5
6
7
8
9
10
11
12
13
14
15
16 to 18
19 to 21
Pin name
PGND1
NC
OUT1
PWM
INA
INB
GND
LGND
GND
DIAG
NC
OUT2
NC
PGND2
VB2
Description
Power GND1
No connect
Internally corrected to TAB1
PWM input
A input
B input
Internally corrected to TAB3
IC GND
Internally corrected to TAB3
Diagnostic output (open drain)
No connect
Internally corrected to TAB2
No connect
Power GND2
MOS FET power supply 2
Pin No.
22
23
24
25
26
27
28
29
30
31
32
33
34 to 36
TAB1
TAB2
TAB3
Pin name
NC
OUT2
NC
VCC
VBS2
GND
V30
GND
VBS1
NC
OUT1
NC
VB1
OUT1
OUT2
GND
Description
No connect
Internally corrected to TAB2
No connect
IC power supply
VB2 sense
Internally corrected to TAB3
IC bias voltage (3.3 V)
Internally corrected to TAB3
VB1 sense
No connect
Internally corrected to TAB1
No connect
MOS FET power supply 1
MOS FET output 1
MOS FET output 2
IC tab GND
R07DS0044EJ0300 Rev.3.00
Sep 01, 2010
PGND1
PGND2
OUT2
Page 2 of 16
R2J25953
Preliminary
Absolute Maximum Ratings
(Ta = 25°C)
Item
Supply voltage
Input voltage
Diag voltage
Output current
Diag current
Junction temperature
Storage temperature
Power temperature
Symbol
VB
Vin
Vdiag
Iout
Idiag
Tj
Tstg
Pt
Ratings
18
–0.3 to VB
–0.3 to VB
50
5
–40 to +150
–55 to +150
40
Unit
V
V
V
A
mA
C
C
W
Note
1
2
3
3
4
Notes: 1. 28 V at 25C, 1 min.
40 V at 25C, 1 sec.
2. Applies to INA, INB, and PWM. Clamps it with 19 V typ.
3. Applies to DIAG
4. One element operation: Tc = 25C
R07DS0044EJ0300 Rev.3.00
Sep 01, 2010
Page 3 of 16
R2J25953
Preliminary
Electrical Characteristics
(Ta = 25°C, VB = VCC = 12 V)
Item
Supply current
VB
MOS
Input current
Static High-side
resistance
Static Low-side
resistance
Off state current
Input current
High threshold
Low threshold
Delay time
Rise time
Fall time
DIAG
Symbol
Icc0
Icc
IinvbL
RonH
RonL
Ioff
IinL
IinH
Vthin
Vtlin
tpLH
tpHL
tr
tf
VDiag
Min
—
—
—
—
—
—
—
—
3.0
—
—
—
—
—
—
Typ
30
3.5
—
9
7
10
—
—
—
—
1.5
3.0
1.0
1.0
0.4
Max
50
10
1
16
11
20
10
10
—
1.5
4.0
6.0
3.0
3.0
0.6
10
—
—
39.1
28.7
5.6
0.7
—
20
1.3
1.3
Unit
A
mA
A
m
m
A
A
A
V
V
s
s
s
s
V
A
°C
°C
V
V
V
V
A
s
V
V
Condition
Standby
ACTIVE
Standby
Iout = 15 A
Pulse test
Iout = 15 A
Pulse test
Vin = 0 V
Vin =VB
Application
terminal
VCC
VB1/VB2
Note
1
1
1
IN
INA/INB
/PWM
OUT/IN (PWM)
OUT
I = 2 mA,
DIAG = Low
Vdiag = 0 V
OUT, PWM
OUT1/2
DIAG
2
Output voltage
Leak current
IDiag
—
—
TSD
Shut-down
Tsd
150
175
temperature
Hysteresis
Thys
7
25
OVD
Shut-down
VtvH
28.9
34
voltage
Return voltage
VtvL
21.3
25
LVI
Return voltage
VRLVI
5.0
5.35
Hysteresis
VHLVI
0.3
0.5
Overcurrent Shut-down
IcL
35
—
detection
current
Detection time
tcL
60
10
MOS FET
Pch forward
VDFp
—
1.0
Body-diode voltage
Nch forward
VDFn
—
1.0
voltage
Notes: 1. Refer to truth table.
2. Refer to the input condition to the truth table.
PWM
50%
3
VCC
VCC
OUT1/2
IF = 50 A,
Pulse test
50%
tpLH
tpHL
90%
90%
50%
10%
OUT1
(OUT2)
10%
50%
tr
tf
3. It is a design guaranteed value, and it doesn't apply to the final test.
R07DS0044EJ0300 Rev.3.00
Sep 01, 2010
Page 4 of 16
R2J25953
Preliminary
Truth table
The operation of OUT1, OUT2, and DIAG is shown in the following.
PWM
High
Input
INA
High
Status
INB
LVI
OVD
Overcurrent
detection
off
off
off
off
off
off
off
Protection circuit doesn't operate
on
x
x
x
off
on
x
x
off
x
on
x
x
x
on
TSD
OUT1
High
High
Low
Low
Hi-z
Hi-z
Low
Low
Hi-z
Hi-z
Hi-z
(Latch)
Hi-z
Output
OUT2
High
Low
High
Low
Hi-z
Low
Hi-z
Low
Hi-z
Hi-z
Hi-z
(Latch)
Hi-z
DIAG
High
High
High
High
High
High
High
High
High
Low
Low
(Latch)
Low
ACTIVE
State
High
Low
Low
High
Low
Low
High
High
Low
Low
High
Low
Excluding All = Low
At least one of PWM,
INA, and INB is high.
STANDBY
LVI
TSD
Overcurrent
detection
OVD
off
Notes 1. x: Regardless of High, Low, on and off.
2. Protect circuit
off = undetection
on = detection
3. State of pin OUT
Low: Nch MOS FET ON, High: Pch MOS FET ON, Hi-z: Nch and Pch MOS FET OFF
4. The latch of overcurrent detection is released when LVI = on or INA = INB = Low.
External Parts List
Parts No.
Cp
R1
C1
Recommended value
10
F
> 10 k
0.033
F
Purpose
Power supply bypass capacitor
Pull up Pin DIAG
Pin V30 bypass capacitor
R07DS0044EJ0300 Rev.3.00
Sep 01, 2010
Page 5 of 16
京公网安备 11010802033920号
EEWORLD
