Bt261
30 MHz Pixel Clock Monolithic
CMOS HSYNC Line Lock Controller
The Bt261 HSYNC Line Lock Controller is designed specifically for image cap-
ture applications.
Either composite video or TTL composite sync information is input via
VIDEO. An internal sync separator separates horizontal and vertical sync infor-
mation. Programmable horizontal and vertical video timing enables recovery of
both standard and nonstandard timing information.
An external VCO may be used in conjunction with the on-chip phase com-
parator for implementation of clocks locked to the horizontal frequency.
Alternately, a high-speed clock (OSC) may be divided down to generate the
pixel clock. The phase of the generated pixel clock is adjusted to align with the
noise-gated CSYNC. The higher the OSC clock rate, the lower the pixel clock
jitter (the maximum being one half the OSC clock period). The OSC inputs may
be configured to be either TTL or ECL compatible. Thus, four TTL clocks, two
TTL clocks and one differential ECL clock, or two differential ECL clocks may
be used. The ECL clock inputs are designed to be driven by 10KH ECL using a
single +5 V supply.
The CLAMP and ZERO outputs are programmed by the MPU to DC restore
the video signal and to zero the Image Digitizer or A/D converter at the appro-
priate time.
Distinguishing Features
• Programmable 12-bit Video Timing
• Bidirectional HSYNC and CLOCK
Pins
• Horizontal Sync Noise Gating
• External VCO Support
• Standard MPU Interface
• TTL Compatible
• + 5 V Monolithic CMOS
• 28-pin PLCC Package
• Typical Power Dissipation:
300˙mW
Applications
•
•
•
•
Image Processing
Video Digitizing
Desktop Publishing
Graphic Art Systems
Functional Block Diagram
Noise-Gated CSYNC*
HSYNC
OSC1
OSC1*
OSC2
OSC2*
M
U
X
XTAL OSC to
Pixel Clock
Generator
Phase
Comparator
PCOUT
CLOCK
3-State
Buffer
Horizontal
Counter
Horizontal
VIDEO
SYNC
Detect
SYNC
Noise Gate
Video
Timing
Control
ZERO
CLAMP
HSYNC
CAPTURE
Vertical
SYNC
Processor
VSYNC*
FIELD
CSYNC*
D0–D7
RD*
WR*
A0
Brooktree
®
Brooktree Division • Rockwell Semiconductor Systems, Inc. • 9868 Scranton Road • San Diego, CA 92121-3707
619-452-7580 • 1-800-2-BT-APPS • FAX: 619-452-1249 • Internet: apps@brooktree.com • L261_H
Ordering Information
Model Number
Bt261KPJ
Package
28-pin Plastic J-lead
Ambient Temperature Range
0
°
to +70
°
C
Copyright © 1997 Brooktree Corporation. All rights reserved.
Print date: September 1993
Brooktree reserves the right to make changes to its products or specifications to improve performance, reliability, or
manufacturability. Information furnished by Brooktree Corporation is believed to be accurate and reliable. However, no
responsibility is assumed by Brooktree Corporation for its use; nor for any infringement of patents or other rights of third parties
which may result from its use. No license is granted by its implication or otherwise under any patent or patent rights of Brooktree
Corporation.
Brooktree products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a
Brooktree product can reasonably be expected to result in personal injury or death. Brooktree customers using or selling Brooktree
products for use in such applications do so at their own risk and agree to fully indemnify Brooktree for any damages resulting from
such improper use or sale.
Brooktree is a registered trademark of Brooktree Corporation. Product names or services listed in this publication are for
identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks
mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
T
ABLE OF
C
ONTENTS
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vi
Circuit Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
MPU Interface
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Video Input / Sync Detector
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Horizontal Counter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Horizontal Sync Separation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
HSYNC Input/Output
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
VSYNC* Output
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
FIELD Output
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CLAMP and ZERO Outputs
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Capture Output
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
External VCO Pixel Clock Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Phase/Frequency Detector Operation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Two Forms of Noise Gating Available
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
The Status Registers SR00 and SR05 Used in Automatic Phase Limiting
. . . . . . . 15
Asynchronous (Unlocked) Pixel Clock Generation
. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pin Descriptions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Internal Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Horizontal Counter
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Command Register_0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Command Register_1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Command Register_2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Command Register_3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VSYNC Sample Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
OSC Count Low and High Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Status Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
HSYNC Start and Stop Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
CLAMP Start and Stop Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
ZERO Start and Stop Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
FIELD Gate Start and Stop Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Noise Gate Start and Stop Registers
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Brooktree
®
L261_H
iii
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
HCOUNT Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Application Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Phase Locking With the 74HC4046
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Interfacing to the Bt218
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Interfacing to the Bt252
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Interfacing to the Bt254
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
ESD and Latchup Considerations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Parametric Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
DC Electrical Parameters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC Electrical Parameters
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing Waveforms
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Revision History
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Brooktree
®
L261_H
iv
Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
Brooktree
®
L261_H
v
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