IS24C01B IS24C02B
TABLE Of COnTEnTS
features ……………………………………………………….…………….................3
Description ………………………………………………...……………….................3
functional Block Diagram ……………………………………………….................4
Pin Configuration & Description ………………………………………..................5
Device Operations …..…………………………………………………….................6
Absolute Maximum Ratings ……………………………………………..................14
Operating Range …………………………………………………………..................14
DC Characteristics ………………………………………………………...................15
AC Characteristics ………………………………………………………...................15
Ordering Information ……………………………………………………...................17
Packaging Information ….………………………………………………...................18
Revision History ……….…………………………………………………..................23
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
06/27/08
IS24C01B IS24C02B
1K-bit/2K-bit
2-WIRE SERIAL CMOS EEPROM
fEATURES
• Two-Wire Serial Interface, I
2
C
TM
compatible
– Bi-directional data transfer protocol
• Wide Voltage Operation
– Vcc = 1.8V to 5.5V
• 400 KHz (2.5V) and 1 MHz (5.0V) compatibility
• Low Power
– Standby Current: 1 µA or less (1.8V)
– Read Current: 2 mA or less (5.0V)
– Write Current: 3 mA or less (5.0V)
• Hardware Data Protection
– Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
5 ms max. @ 2.5V
• Memory Organization:
– IS24C01B: 128x8 (1K bits)
– IS24C02B: 256x8 (2K bits)
• 8 Byte Page Write Buffer
• High Reliability
– Endurance: 1,000,000 Cycles
– Data Retention: 100 Years
• Industrial and Automotive temperature ranges
• Packages: SOIC/SOP, TSSOP, PDIP, DFN, and
CSP
DESCRIPTIOn
The IS24C01B and IS24C02B are EEPROM de-
vices that use the industrial standard 2-wire, I
2
C,
interface for communications. The IS24C01B and
IS24C02B contain a memory array of 1K-bits (128
x 8) and 2K-bits (256 x 8), respectively. Each de-
vice is organized into 8 byte pages for page write
mode.
This EEPROM operates in a wide voltage range of
1.8V to 5.5V to be compatible with most applica-
tion voltages. ISSI designed this device family to
be a practical, low-power 2-wire EEPROM solution.
The devices are offered in lead-free, RoHS, halo-
gen free or Green. The available package types are
8-pin SOIC, TSSOP, PDIP, DFN, and CSP.
The IS24C01B/02B maintains compatibility with
the popular 2-wire bus protocol, so it is easy to
use in applications implementing this bus type.
The simple bus consists of the Serial Clock wire
(SCL) and the Serial Data wire (SDA). Using the
bus, a Master device such as a microcontroller is
usually connected to one or more Slave devices
such as this device. The bit stream over the SDA
line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address
within that Slave device, and a series of data, if ap-
propriate. The IS24C01B/02B has a
Write Protect pin (WP) to allow blocking of any
write instruction transmitted over the bus.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
06/27/08
3
IS24C01B IS24C02B
PIN CONFIGURATION
8-Pin SOIC, TSSOP, PDIP
8-pad Dfn
A0
A1
A2
GND
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0 1
A1 2
A2 3
GND 4
8 VCC
7 WP
6 SCL
5 SDA
(Top View)
PIn DESCRIPTIOnS
A0-A2
SDA
SCL
WP
Vcc
GND
Address Inputs
Serial Address/Data I/O
Serial Clock Input
Write Protect Input
Power Supply
Ground
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses
and data into and out of the device. The SDA pin is an open
drain output and can be wire-Or'ed with other open drain or
open collector outputs. The SDA bus
requires
a pullup resistor
to Vcc.
A0, A1, A2
The A0, A1 and A2 are the device address inputs. The
IS24C01B/02B uses the A0, A1, and A2 for hardware addressing
and a total of 8 devices may be used on a single bus system.
When the A0, A1, or A2 inputs are left floating, the input
internally defaults to zero.
WP
WP is the Write Protect pin. If the WP pin is tied to V
cc
on
the EEPROM, the entire array becomes Write Protected
(Read only). When WP is tied to GND or left floating normal
read/write operations are allowed to the device.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. D
06/27/08
5
京公网安备 11010802033920号
EEWORLD
