IDT10484S8Y datasheet, PDF - EEWORLD Datasheet

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IDT10484S8Y: DescriptionStandard SRAM, 4KX4, 8ns, PDSO24; Categorystorage storage; File Size96KB，7 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT10484S8Y Overview

Standard SRAM, 4KX4, 8ns, PDSO24

IDT10484S8Y Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Reach Compliance Code	not_compliant
Maximum access time	8 ns
I/O type	SEPARATE
JESD-30 code	R-PDSO-J24
JESD-609 code	e0
memory density	16384 bit
Memory IC Type	STANDARD SRAM
memory width	4
Humidity sensitivity level	3
Negative supply voltage rating	-5.2 V
Number of terminals	24
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4KX4
Output characteristics	OPEN-EMITTER
Package body material	PLASTIC/EPOXY
encapsulated code	SOJ
Encapsulate equivalent code	SOJ24,.34
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	-5.2 V
Certification status	Not Qualified
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30

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HIGH-SPEED BiCMOS

ECL STATIC RAM

16K (4K x 4-BIT) SRAM

Integrated Device Technology, Inc.

PRELIMINARY

IDT10484, IDT10A484

IDT100484, IDT100A484

IDT101484, IDT101A484

FEATURES:

• 4096-words x 4-bit organization

• Address access time: 4/4.5/5/7/8/10/15 ns

• Low power dissipation: 900mW (typ.)

• Guaranteed Output Hold time

• Fully compatible with ECL logic levels

• Separate data input and output

• Corner and Center power pin pinouts

• Standard through-hole and surface mount packages

• Guaranteed-performance die available for MCMs/hybrids

• MIL-STD-883, Class B product available

DESCRIPTION:

The IDT10484(10A484), IDT100484(100A484) and

IDT101484(101A484) are 16,384-bit high-speed BiCEMOS™

ECL static random access memories organized as 4Kx4, with

separate data inputs and outputs. All I/Os are fully compatible

with ECL levels.

These devices are part of a family of asynchronous four-

bit-wide ECL SRAMs. This device is available in both the

traditional corner-power pinout, and "revolutionary" center-

power pin configurations. Because they are manufactured in

BiCEMOS™ technology, power dissipation is greatly reduced

over equivalent bipolar devices. Low power operation pro-

vides higher system reliability and makes possible the use of

the plastic SOJ package for high-density surface mount

assembly.

The fast access time and guaranteed Output Hold time

allow greater margin for system timing variation. DataIN setup

time specified with respect to the trailing edge of Write Pulse

eases write timing allowing balanced Read and Write cycle

times.

FUNCTIONAL BLOCK DIAGRAM

16,384-BIT

MEMORY ARRAY

DECODER

WE1

WE2

SENSE AMPS

AND READ/WRITE

CONTROL

2811 drw 01

BiCEMOS is a trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

Integrated Device Technology, Inc.

JANUARY 1992

DSC-8018/4

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