Integrated
Circuit
Systems, Inc.
ICS83841
20 B
IT
, DDR SDRAM 2:1 MUX
F
EATURES
•
Forty low skew single-ended DIMM ports
•
One SSTL-2 compatible select input
•
Maximum Switching Speed: 3ns
•
Output skew: 180ps (maximum)
•
r
on
= 20Ω (typical)
•
Full 2.5V supply modes
•
0°C to 70°C ambient operating temperature
•
Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS83841 is a 20 Bit, DDR SDRAM 2:1 MUX
and is a member of the HiPerClockS™ family of
HiPerClockS™
High Performance Clock Solutions from ICS. The
device has 20 host lines and each host line can
be passed to 2 data ports. The host/data ports
are compatible with single-ended SSTL-2 and the device op-
erates from a 2.5V supply.
IC
S
Guaranteed low output skew makes the ICS83841 ideal for
demanding applications which require well defined performance
and repeatability.
S
IMPLIFIED
S
CHEMATIC
L
OGIC
D
IAGRAM
DH0
r
on
Sw
Sw
DA0
DB0
DHx
DAx or DBx
R
PD
DH19
r
on
Sw
Sw
DA19
DB19
S
S
SW
P
IN
A
SSIGNMENT
1
A
B
C
D
E
F
G
H
J
K
DB
17
DA
18
DB
18
DA
19
DB
19
DA
0
DB
0
DA
1
DB
1
DA
2
2
DA
17
DH
17
DH
18
GND
DH
19
DH
0
GND
DH
1
DH
2
DB
2
3
DB
16
DH
16
4
DB
15
DA
16
5
DA
15
DH
15
GND
6
DB
14
DH
14
GND
7
DA
14
DB
13
8
DA
13
DH
13
9
DB
12
DH
12
DH
11
GN D
10
DA
12
DB
11
DA
11
DB
10
DA
10
DB
9
DA
9
DB
8
DA
8
DB
7
REV. A JANUARY 20, 2006
ICS83841
72-Ball TFBGA
6mm x 6mm x 1.2mm
package body
H Package
Top View
S
V
DD
GND
DH
3
DA
3
DB
3
DA
4
DH
4
DB
4
GN D
DH
5
DA
5
DA
6
DB
5
V
DD
V
DD
DH
10
DH
9
GN D
DH
8
DH
6
DB
6
DH
7
DA
7
83841BH
www.icst.com/products/hiperclocks.html
1
Integrated
Circuit
Systems, Inc.
ICS83841
20 B
IT
, DDR SDRAM 2:1 MUX
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
E8, F3, F8
C5, C6, D2, D9, G2, G9, H5, H6
E3
B2, B3, B5, B6, B8, B9,
C2 C9, E2, E9, F2, F9, H2,
H9, J2, J3, J5, J6, J8, J9
A2, A5, A7, A8, A10, B1,
B4, C10, D1, E10, F1, G10, H1,
J7, J10, K1, K3, K4, K6, K9
A1, A3, A4, A6, A9, B7,
B10, C1, D10, E1, F10, G1, H10,
J1, J4, K2, K5, K7, K8, K10
Name
V
DD
GND
S
DH17, DH16, DH15, DH14, DH13, DH12,
DH18, DH11, DH19, DH10, DH0, DH9, DH1,
DH8, DH2, DH3, DH4, DH5, DH6, DH7
DA17, DA15, DA14, DA13, DA12, DA18,
DA16, DA11, DA19, DA10, DA0, DA9, DA1,
DA6, DA8, DA2, DA3, DA4, DA5, DA7
DB17, DB16, DB15, DB14, DB12, DB13,
DB11, DB18, DB10, DB19, DB9, DB0, DB8,
DB1, DB3, DB2, DB4, DB5, DB6, DB7
Type
Description
Power Positive supply pins.
Power Power supply ground.
Control Input. Selects Host
Input
Por t function per Table 3.
Por t
Host por ts.
Por t
DIMM por ts.
Por t
DIMM por ts.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol Parameter
C
IN
C
ON
Control Pin Capacitance
Channel on Capacitance
Test Conditions
V
I
= 0V or V
DD
V
IN
= 1.5V
Minimum
Typical
Maximum
5
10
Units
pF
pF
T
ABLE
3. F
UNCTION
T
ABLE
Control Input
S
L
H
Function
Host Por t = B DIMM Por ts
A DIMM Por t = 140
Ω
to GND
Host Por t = A DIMM Por ts
B DIMM Por t = 140
Ω
to GND
83841BH
www.icst.com/products/hiperclocks.html
2
REV. A JANUARY 20, 2006
Integrated
Circuit
Systems, Inc.
ICS83841
20 B
IT
, DDR SDRAM 2:1 MUX
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Ports
DC Input Clamp Current, I
IK
-50mA
-0.5V to +3.3V
-0.3V to V
DD
+ 0.3 V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Package Thermal Impedance,
θ
JA
50.04°C/W (0 mps)
Storage Temperature, T
STG
-65°C to 150°C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 0.2V, T
A
= 0°C
TO
70°C
Symbol Parameter
V
DD
I
DD
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.3
Typical
2.5
20
Maximum
2.7
Units
V
µA
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= 2.5V ± 0.2V, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
V
IK
I
L
Input High Voltage
Input Low Voltage
Input Clamp Voltage
S
Input Leakage
Current
Host Por t
DIMM Por t
r
ON
On Resistance; NOTE 1
S
S
V
DD
= 2.3V; I
I
= -18mA
V
DD
= 2.5V; V
I
= V
DD
or GND;
S = V
DD
S = GND for I
IL(test)
V
DD
= 2.5V; V
A
= 0.8V; V
B
= 1.0V
16
20
Test Conditions
Minimum
1.6
0.9
-1.2
±100
±100
±100
30
Typical
Maximum
Units
V
V
V
µA
µA
µA
Ω
Ω
16
20
30
V
DD
= 2.5V; V
A
= 1.7V; V
B
= 1.5V
NOTE 1: Measured by the current between the Host and the DIMM terminals at the indicated voltages on each side
of the switch.
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= 2.5V ± 0.2V, T
A
= 0°C
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Propagation Delay;
From DHx or DAx/DBx
125
240
ps
t
PD
NOTE 1, 3
to DAx/DBx or DHx
Output
From S to
1.2
ns
t
EN
Enable Time
DHx or DAx/DBx
Output
From S to
1.2
ns
t
DIS
Disable Time
DHx or DAx/DBx
Output Skew;
Any Por t to any Por t
180
ps
t
OSK
NOTE 2, 3
NOTE 1: Measured from V
DD
/2 of the input to V
DD
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
NOTE 3: Not production tested, guaranteed by characterization.
83841BH
www.icst.com/products/hiperclocks.html
3
REV. A JANUARY 20, 2006
Integrated
Circuit
Systems, Inc.
ICS83841
20 B
IT
, DDR SDRAM 2:1 MUX
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
DD
= 1.25V ± 0.1V
V
DD
SCOPE
DAx,
DBx
V
DD
2
LVCMOS
GND
Qx
V
DD
DAy,
DBy
2
tsk(o)
-1.25V ± 0.1V
This circuit is used for test purposes only,
not
intended for application use.
2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
O
UTPUT
S
KEW
2.5V
1.25V
Input
Rising Edge
Skew
1.25V
Output
1.25V
0V
FallingEdge
Skew
V
OH
1.25V
V
OL
S
(Low-level
enabling)
2.5V
1.25V
1.25V
0V
t
PZH
→
Output DAx/DBx
(See Note)
1.25V
t
PHZ
→
←
V
OH
V
OH
- 0.15V
V
OL
NOTE: The output is high except when disabled by the S control.
R
ISING
& F
ALLING
E
DGE
S
KEW
3-S
TATE
O
UTPUT
E
NABLE
/D
ISABLE
T
IMES
DAx
V
DD
2
DHx
V
DD
2
DBx
V
DD
2
tsk(b)
DAx/DBx
t
PD
V
DD
2
B
ANK
S
KEW
83841BH
P
ROPAGATION
D
ELAY
www.icst.com/products/hiperclocks.html
4
REV. A JANUARY 20, 2006
Integrated
Circuit
Systems, Inc.
ICS83841
20 B
IT
, DDR SDRAM 2:1 MUX
R
ELIABILITY
I
NFORMATION
T
ABLE
6.
θ
JA
VS
. A
IR
F
LOW
T
ABLE
FOR A
72-B
ALL
TFBGA
θ
JA
by Velocity (Millimeter Feet per Second)
0
Two-Layer PCB, JEDEC Standard Test Boards
50.04°C/W
1
43.18°C/W
2
41.17°C/W
NOTE:
Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
T
RANSISTOR
C
OUNT
The transistor count for ICS83841 is: 261
83841BH
www.icst.com/products/hiperclocks.html
5
REV. A JANUARY 20, 2006
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