Integrated
Circuit
Systems, Inc.
ICS91309
High Performance Communication Buffer
General Description
The
ICS91309
is a high performance, low skew, low jitter
zero delay buffer. It uses a phase lock loop (PLL)
technology to align, in both phase and frequency, the REF
input with the CLKOUT signal. It is designed to distribute
high speed clocks in communication systems operating
at speeds from 10 to 133 MHz.
The
ICS91309
provides synchronization between the
input and output. The synchronization is established via
CLKOUT feed back to the input of the PLL. Since the skew
between the input and output is less than +/- 350 pS, the
part acts as a zero delay buffer.
ICS91309
has two banks of four outputs controlled by two
address lines. Depending on the selected address line,
bank B or both banks can be put in a tri-state mode. In this
mode, the PLL is still running and only the output buffers
are put in a high impedance mode. The test mode shuts
off the PLL and connects the input directly to the output
buffers (see table below for functionality).
ICS91309
comes in a 16-pin 150 mil SOIC, SSOP or
4.40mm TSSOP package. In the absence of REF input,
the device will enter a powerdown mode. In this mode, the
PLL is turned off and the output buffers are pulled low.
Power down mode provides the lowest power consumption
for a standby condition.
Features
•
•
•
•
•
•
•
•
•
•
Zero input - output delay
Frequency range 10 - 133 MHz (3.3V)
5V tolerant input REF
High loop filter bandwidth ideal for Spread Spectrum
applications.
Less than 125 ps cycle to cycle Jitter
Skew controlled outputs
Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm
TSSOP packages
Skew: Group-to-Group: <215 ps
Skew within Group: <100 ps
Commercial temperature range: 0°C to +70°C
Pin Configuration
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
FS2
1
2
16
15
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
FS1
4
5
6
7
8
ICS91309
3
14
13
12
11
10
9
Block Diagram
16 pin SSOP, SOIC & TSSOP
Functionality
FS2 FS1 CLKA(1:4) CLKB(1:4) CLKOUT
0
0
1
1
0
1
0
1
Tristate
Driven
PLL
Bypass
Mode
Driven
Tristate
Tristate
PLL Bypass
Mode
Driven
Driven
Driven
PLL
Bypass
Mode
Driven
Ouput
PLL
Source Shutdown
PLL
N
PLL
N
REF
PLL
Y
N
0093G—02/11/04
ICS91309
Pin Descriptions
PIN # PIN NAME
1
REF
1
2
CLKA1
2
3
CLKA2
2
4, 13 VDD
5, 12 GND
6
CLKB1
2
7
CLKB2
2
8
FS2
3
9
FS1
3
10 CLKB3
2
11 CLKB4
2
14 CLKA3
2
15 CLKA4
2
16 CLKOUT
2
Notes:
1. Weak pull-down
2. Weak pull-down on all outputs
3. Weak pull-ups on these inputs
PIN TYPE
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
DESCRIPTION
Input reference frequency, 5V tolerant input
Buffered clock output, Bank A
Buffered clock output, Bank A
Power Supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Function select input, bit 2
Function select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output, internal feedback
0093G—02/11/04
2
ICS91309
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs (Except REF) . . . . . . . . . . . . . . GND –0.5 V to V
DD
+ 0.5 V
Logic Input REF . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to GND + 5.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input & Supply
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-10%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input High Current
I
IH
V
IN
= V
DD
I
IL
V
IN
= 0 V
Input Low Current
Output High Voltage
Vo
H
Io
H
= -12 mA
Output Low Voltage
Vo
L
Io
L
= 12 mA
Operating Supply
I
DD
Outputs Unloaded; REF = 66 MHz
Current
Powerdown Current
Input Frequency
Input Capacitance
1
MIN
2
TYP
MAX
0.8
100
50
0.4
0.1
19
2.4
UNITS
V
V
uA
uA
V
V
mA
uA
MHz
pF
30
0.3
10
45
12
133
5
I
DD
F
i
C
IN
REF = 0 Mhz
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
0093G—02/11/04
3
ICS91309
Electrical Characteristics - Outputs
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-10%; C
L
= 30 pF (unless otherwise specified)
PARAMETER
Output High Voltage
Output Low Voltage
Rise Time
1
Fall Time
PLL Lock Time
1
Output Frequency
Duty Cycle
1
1
1
Jitter, Cycle-to-cycle
Jitter, Absolute
1
Jitter, 1-Sigma
1
1
Skew, Group-to-Group
Skew, Output-to-Output
1
Skew, Device-to-Device
1
Delay, Input-to-Output
1
SYMBOL
V
OH
V
OL
t
r
t
f
T
LOCK
f
1
f
1
Dt1
Dt2
t
jcyc-cyc
Tjabs
Tj1s
Tsk
Tsk
Tdsk-Tdsk
Dr1
CONDITIONS
I
OH
= -12 mA
I
OL
= 12 mA
Measure between 0.8 V and 2.0 V
Measure between 2.0 V and 0.8 V
Stable V
DD
, valid clock on REF
C
L
= 30 pF
C
L
= 10 pF
Measured at 1.4 V, Fout = 66.7 MHz
Measured at V
DD
/2, Fout < 50.0 MHz
Measured at 66.7 MHz, loaded outputs
10,000 cycles, C
L
= 30 pF
10,000 cycles, C
L
= 30 pF
Measured at 1.4 V
Measured at 1.4 V, within a group
Measured at V
DD
/2,on CLKOUT pins
Measured at 1.4 V
MIN
2.4
TYP
MAX
0.4
1.5
1.5
1
100
133
60
55
125
100
30
215
100
700
700
1.2
1.2
10
10
40
45
-100
50
50
70
14
UNITS
V
V
ns
ns
mS
MHz
MHz
%
%
ps
ps
ps
ps
ps
ps
ps
Notes:
1. Guaranteed by design and characterization, not 100% tested in production.
0093G—02/11/04
4
ICS91309
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one
of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded,
zero phase difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded
than CLKOUT, CLKA/B will lag the CLKOUT.
Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them
to have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLKA/B
outputs loaded equally, with
CLKOUT loaded Less.
0093G—02/11/04
Timing diagrams with different loading configurations
5
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