SiP21101
Vishay Siliconix
150-mA Ultra Low-Noise LDO Regulator With Discharge
FEATURES
D
Ultra Low Dropout—130 mV at 150-mA Load
D
Ultra Low Noise—30
mV
(rms)
(10-Hz to 100-kHz
Bandwidth)
D
Shutdown Control
D
110-mA Ground Current at 150-mA Load
D
1.5% Guaranteed Output Voltage Accuracy
D
300-mA Peak Output Current Capability
D
Uses Low ESR Ceramic Capacitors
D
Fast Start-Up (50
ms)
D
Fast Line and Load Transient Response (v 30
ms)
D
1-mA Maximum Shutdown Current
D
Output Current Limit
D
Reverse Battery Protection
D
Built-in Short Circuit and Thermal Protection
D
Output, Auto-Discharge In Shutdown Mode
D
Fixed 1.2, 1.8, 2.5, 2.6, 2.8, 2.85, 3.0, 3.3, 5.0-V Output
Voltage Options
D
SC70-5 Package
RoHS
COMPLIANT
Available
APPLICATIONS
D
Cellular Phones, Wireless Handsets
D
Noise-Sensitive Electronic Systems, Laptop and
Palmtop Computers
D
PDAs
D
Pagers
D
Digital Cameras
D
MP3 Player
D
Wireless Modem
DESCRIPTION
The SiP21101 is a 150-mA CMOS LDO (low dropout) voltage
regulator. It is the perfect choice for low voltage, low power
applications. An ultra low ground current makes this part
attractive for battery operated power systems. The SiP21101
also offers ultra low dropout voltage to prolong battery life in
portable electronics. Systems requiring a quiet voltage
source, such as RF applications, will benefit from the
SiP21101’s ultra low output noise. An external noise bypass
capacitor connected to the device’s BP pin can further reduce
the noise level. The SiP21101 is designed to maintain
regulation while delivering 300-mA peak current, making it
ideal for systems that have a high surge current upon turn-on.
For better transient response and regulation, an active
pull-down circuit is built into the SiP21101 to clamp the output
voltage when it rises beyond normal regulation. The SiP21101
automatically discharges the output voltage by connecting the
output to ground through a 100-W n-channel MOSFET when
the device is put in shutdown mode.
The SiP21101 features reverse battery protection to limit
reverse current flow to approximately 1-mA in the event
reversed battery is applied at the input, thus preventing
damage to the IC.
The SiP21101 is available in a lead (Pb)-free 5-pin SC70
package for operation over the industrial operating range
(−40
_C
to 85
_C).
TYPICAL APPLICATION CIRCUIT
SiP21101
V
IN
1
mF
2
GND
1
V
IN
V
OUT
5
V
OUT
1
mF
SD
3
SD
BP
4
10 nF
SC70, 5-Lead
Document Number: 73212
S-51148—Rev E, 20-Jun-05
www.vishay.com
1
SiP21101
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings
Input Voltage, V
IN
to GND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−6.0
to 6.5 V
V
SD
(See Detailed Description)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−0.3
V to V
IN
Output Current, I
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short Circuit Protected
Output Voltage, V
OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−
0.3 V to V
IN
+ 0.3 V
Package Power Dissipation, (P
d
)
b
. . . . . . . . . . . . . . . . . . . . . . . . . . . 384 mW
Package Thermal Resistance, (q
JA
)
a
. . . . . . . . . . . . . . . . . . . . . . . . . 207_C/W
Maximum Junction Temperature, T
J(max)
. . . . . . . . . . . . . . . . . . . . . . . 150_C
Storage Temperature, T
STG
. . . . . . . . . . . . . . . . . . . . . . . . . .
−65_C
to 150_C
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 4.8 mW/_C above T
A
= 70_C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Input Voltage, V
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V to 6 V
Input Voltage, V
SD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
IN
C
IN
= C
OUT
= 1
mF
(ceramic), C
BP
= 0.01
mF
(ceramic)
Maximum ESR of C
OUT
: 0.4
W
Operating Ambient Temperature, T
A
. . . . . . . . . . . . . . . . . . . .
−40_C
to 85_C
SPECIFICATIONS
Test Conditions Unless Specified
Parameter
Start-Up BP Current
Input Voltage Range
Output Voltage Accuracy
Line Regulation (V
OUT
v
3 V)
Line Regulation
(3.0 V < V
OUT
v3.6
V)
Line Regulation (5-V Version)
DV
OUT
DV
IN
100
From V
IN
= V
OUT(nom)
+ 1 V to V
OUT(nom)
+ 2 V
V
OUT(nom)
From V
IN
= 5.5 V to 6 V
I
OUT
= 1 mA
d,
Dropout V lt
D
t Voltage
d g
(V
OUT(nom)
w
2.6 V)
Limits
−40
to 85_C
Symbol
I
OUT
V
IN
V
OUT
T
A
= 25_C, V
IN
= V
OUT(nom)
+ 1 V, I
OUT
= 1 mA,
C
IN
= 1
mF,
C
OUT
= 1.0
mF,
V
SD
= 1.5 V
Temp
a
Room
Full
Min
b
Typ
c
1
Max
b
Unit
mA
ON/OFF = High
2
−1.5
−2.5
−0.06
0
0
1
45
50
130
65
190
100
110
110
120
300
1
1
6
1.5
2.5
0.18
0.3
0.4
V
%
1 mA
v
I
OUT
v
150 mA
Room
Full
Full
Full
Full
Room
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
Full
%/V
I
OUT
= 50 mA
I
OUT
= 150 mA
I
OUT
= 50 mA
I
OUT
= 150 mA
I
OUT
= 0 mA
I
OUT
= 150 mA
I
GND
I
OUT
= 0 mA
I
OUT
= 150 mA
I
O(peak)
V
OUT
w
0.95 x V
OUT(nom)
. t
PW
= 2 ms
80
90
180
220
100
120
250
300
150
180
200
230
170
200
200
230
mA
Document Number: 73212
S-51148—Rev E, 20-Jun-05
mA
mV
V
IN
−
V
OUT
Dropout
(V
OUT(
2.6 V
OUT(nom)
t
2 6 V, V
IN
w
)
2 V)
Voltage
d, g
Ground Pin Current
e, g
(V
OUT(nom)
v
3 V)
Ground Pin Current
e
(V
OUT(nom)
u
3 V)
Peak Output current
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SiP21101
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified
Parameter
Symbol
T
A
= 25_C, V
IN
= V
OUT(nom)
+ 1 V, I
OUT
= 1 mA,
C
IN
= 1
mF,
C
OUT
= 1.0
mF,
V
SD
= 1.5 V
Limits
−40
to 85_C
Temp
a
Room
Room
Room
Room
Room
Room
Room
Room
Room
Min
b
Typ
c
300
30
60
40
30
20
20
150
20
1
700
Max
b
Unit
Output Noise Voltage
e
N
V
NOM
= 2.6 V
BW = 10 Hz to 100 kHz
kHz,
0 mA
t
I
OUT
t
150 mA
I
OUT
= 150 mA
without C
BP
C
BP
= 0.01
mF
f = 1 kHz
f = 10 kHz
f = 100 kHz
mV(rms)
Ripple Rejection
pp
j
DV
OUT
/DV
IN
dB
Dynamic Line Regulation
Dynamic Load Regulation
Thermal Shutdown Junction
Temperature
Thermal Hysteresis
Reverse current
Short Circuit Current
DV
O(line)
DV
O(load)
T
J(S/D)
T
HYST
I
R
I
SC
V
IN
: V
OUT(nom)
+ 1 V to V
OUT(nom)
+ 2 V
t
r
/t
f
= 2
ms,
I
OUT
= 150 mA
I
OUT
: 1 mA to 150 mA, t
r
/t
f
= 2
ms
mV
_C
C
mA
mA
V
IN
=
−6.0
V
V
OUT
= 0 V
Room
Room
Shutdown
Shutdown Supply Current
SD Pin Input Voltage
Auto Discharge Resistance
SD Pin Input Current
f
SD Hysteresis
V
OUT
Turn-On Time
I
CC(off)
V
SD
R_DIS
I
IN(SD)
V
HYST(SD)
t
ON
V
SD
(See Figure 1), I
LOAD
= 100 nA
V
SD
= 0 V
High = Regulator ON (Rising)
Low = Regulator OFF (Falling)
SiP21101 Only
V
SD
= 1.5 V, V
IN
= 6 V
Room
Full
Full
Room
Room
Full
100
0.7
150
50
1.5
0.1
1
V
IN
0.4
mA
V
W
mA
mV
mS
Notes
a. Room = 25_C, Full =
−40
to 85_C.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Typical values for dropout voltage at V
OUT
w
2 V are measured at
V
OUT
= 3.3 V, while typical values for dropout voltage at V
OUT
< 2 V are measured at V
OUT
= 1.8 V.
d. Dropout voltage is defined as the input to output differential voltage at which the output voltage drops 2% below the output voltage measured with a 1-V
differential, provided that V
IN
does not not drop below 2.0 V.
e. Ground current is specified for normal operation as well as “drop-out” operation.
f.
The device’s shutdown pin includes a typical 2-MW internal pull-down resistor connected to ground.
g. V
OUT(nom)
is V
OUT
when measured with a 1-V differential to V
IN.
TIMING WAVEFORMS
V
IN
V
SD
t
r
v
1
ms
0V
t
ON
V
NOM
0.95 V
NOM
V
OUT
FIGURE 1.
Timing Diagram for Power-Up
Document Number: 73212
S-51148—Rev E, 20-Jun-05
www.vishay.com
3
SiP21101
Vishay Siliconix
PIN CONFIGURATION
SC70, 5-Lead
V
IN
1
5
V
OUT
GND
SD
2
BP
3
4
PIN DESCRIPTION
Pin Number
1
2
3
4
5
Name
V
IN
GND
SD
BP
V
OUT
Function
Input supply pin. Bypass this pin with a 1-mF ceramic or tantalum capacitor to ground
Ground pin. For better thermal capability, directly connected to large ground plane
By applying less than 0.4 V to this pin, the device will be turned off. Connect this pin to V
IN
if unused
Noise bypass pin. For low noise applications, a 0.01-mF ceramic capacitor should be connected from this pin to ground.
Output voltage. Connect C
OUT
between this pin and ground.
ORDERING INFORMATION
Part Number
SiP21101DR-12-E3
SiP21101DR-18-E3
SiP21101DR-25-E3
SiP21101DR-26-E3
SiP21101DR-28-E3
SiP21101DR-285-E3
SiP21101DR-30-E3
SiP21101DR-33-E3
SiP21101DR-50-E3
Note: LL = Lot Code
Marking
X0LL
A0LL
A3LL
A4LL
A6LL
A7LL
B0LL
B1LL
B4LL
Voltage
1.2
1.8
2.5
2.6
2.8
2.85
3.0
3.3
5.0
Temp.
Range
Pkg.
−40
to 85_C
SC70-5
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4
Document Number: 73212
S-51148—Rev E, 20-Jun-05
SiP21101
Vishay Siliconix
TYPICAL CHARACTERISTICS (INTERNALLY REGULATED, 25_C UNLESS NOTED)
0.30
0.15
0.00
−0.15
−0.30
−0.45
−0.60
−0.75
0
25
50
75
100
125
150
Load Current (mA)
V
OUT
(%)
Normalized Output Voltage vs. Load Current
V
IN
= V
OUT(nom)
+ 1 V
0.4
0.2
Normalized V
OUT
vs. Temperature
V
IN
= V
OUT(nom)
+ 1 V
I
OUT
= 0 mA
Output Voltage (%)
−0.0
−0.2
−0.4
−0.6
−0.8
−1.0
−40
I
OUT
= 75 mA
I
OUT
= 150 mA
−15
10
35
60
85
Ambient Temperature (_C)
150
GND Current vs. Load Current
V
OUT
= 3.0 V
V
IN
= 4.0 V
300
250
200
I
GND
(
mA)
150
100
No Load GND Pin Current vs. Input Voltage
85_C
125
25_C
I
GND
(
mA)
100
−40_C
75
50
50
0
25
50
75
100
125
150
Load Current (mA)
0
2
3
4
5
6
7
Input Voltage (V)
85_C
25_C
−40_C
0
Power Supply Rejection
C
IN
= 1
mF
C
OUT
= 1
mF
I
LOAD
= 150 mA
V
OUT
= 3.0 V
I
SC
(mA)
750
725
700
Output Short Circuit Current vs. Temperature
V
OUT
= 2.6 V
−20
Gain (dB)
−40
675
650
−60
625
−80
10
600
−40
100
1000
10000
100000
1000000
−15
10
35
60
85
Frequency (Hz)
Document Number: 73212
S-51148—Rev E, 20-Jun-05
AmbientTemperature (_C)
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