EA2M
2 Mb SPI Serial CMOS
EEPROM
Description
The EA2M is a 2 Mb Serial CMOS EEPROM device internally
organized as 256Kx8 bits. This features a 256−byte page write buffer
and supports the Serial Peripheral Interface (SPI) protocol. The device
is enabled through a Chip Select (CS) input. In addition, the required
bus signals are clock input (SCK), data input (SI) and data output (SO)
lines. The HOLD input may be used to pause any serial
communication with the EA2M device. The device features software
and hardware write protection, including partial as well as full array
protection. On−Chip ECC (Error Correction Code) makes the device
suitable for high reliability applications.
The EA2M device is designed for ultra−low power consumption,
targeting real−time data logging applications, hearing aids and
other medical devices and battery operated applications.
Features
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WLCSP8
CASE 567GV
PIN CONFIGURATION
Pin 1
V
CC
HOLD
SCK
SI
V
SS
CS
SO
WP
•
•
•
•
•
•
•
•
•
•
•
•
•
5 MHz SPI Compatible
Supply Voltage Range: 1.6 V to 3.6 V
SPI Modes (0,0) & (1,1)
256−byte Page Write Buffer
Additional Identification Page with Permanent Write Protection
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection – Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
WLCSP 8−ball Package, and Die Sales
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
CC
WLCSP8 (Top View)
PIN FUNCTION
Pin Name
CS
SO
WP
V
SS
SI
SCK
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
SI
CS
WP
HOLD
SCK
EA2M
SO
HOLD
V
CC
ORDERING INFORMATION
V
SS
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
Figure 1. Functional Symbol
©
Semiconductor Components Industries, LLC, 2014
1
September, 2014 − Rev. 1
Publication Order Number:
EA2M/D
EA2M
MARKING DIAGRAM
EA2M
ALYWG
G
(WLCSP8)
EA2M = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Operating Temperature
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
0 to +85
–10 to +90
–0.5 to +6.5
Units
°C
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 5)
Symbol
N
END
(Notes 2, 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program/Erase Cycles
Years
2. Page Mode, V
CC
= 5 V, 25°C.
3. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes located at addresses
4N, 4(N+1), 4(N+2), 4(N+3), in order to benefit from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 1.6 V to 3.6 V, T
A
= 0°C to +70°C, unless otherwise specified.)
Symbol
I
CCR
Parameter
Supply Current
(Read Mode)
I
CCW
Supply Current
(Write Mode)
I
SB1
(Note 4)
I
SB2
(Note 4)
I
L
I
LO
V
IL1
V
IH1
V
IL1
V
IH1
V
OL1
V
OH1
V
OL2
V
OH2
Standby Current
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 3.6 V, SO open, f
CLK
= 5 MHz
V
CC
= 1.6 V, SO open, f
CLK
= 5 MHz
V
CC
= 3.6 V
V
CC
= 1.6 V
V
IN
= GND or V
CC
, CS = V
CC
, WP = V
CC
, HOLD = V
CC
V
IN
= GND or V
CC
, CS = V
CC
, WP = GND, HOLD = GND
V
IN
= GND or V
CC
CS = V
CC
, V
OUT
= GND or V
CC
V
CC
≥
2.5 V
V
CC
≥
2.5 V
V
CC
< 2.5 V
V
CC
< 2.5 V
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
≥
2.5 V, I
OH
=
−1.6
mA
V
CC
< 2.5 V, I
OL
= 150
mA
V
CC
< 2.5 V, I
OH
= −100
mA
V
CC
− 0.2
V
CC
− 0.8
0.2
−1
−1
−0.5
0.7 x V
CC
−0.5
0.75 x V
CC
Min
Max
0.8
0.4
1.0
0.7
1
3
1
1
0.3 x V
CC
V
CC
+ 0.5
0.25 x V
CC
V
CC
+ 0.5
0.4
mA
mA
mA
mA
V
V
V
V
V
V
V
V
mA
Units
mA
4. When not driven, the WP and HOLD inputs are pulled up to V
CC
internally. For noisy environments, when the pin is not used, it is
recommended the WP and HOLD input to be tied to V
CC
, either directly or through a resistor.
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EA2M
Table 4. PIN CAPACITANCE
(Note 5) (T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
C
OUT
C
IN
Test
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
8
Units
pF
pF
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
Table 5. A.C. CHARACTERISTICS
(V
CC
= 1.6 V to 3.6 V, T
A
= 0°C to +70°C, unless otherwise specified.) (Note 6)
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 7)
t
FI
(Note 7)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
CNS
t
CNH
t
WPS
t
WPH
t
WC
(Note 8, 10)
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
80
60
60
60
60
20
20
10
0
50
100
0
10
75
Parameter
Min
DC
20
20
75
75
50
2
2
Max
5
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 6. POWER−UP TIMING
(Notes 7, 9)
Symbol
t
PUR,
t
PUW
Parameter
Power−up to Read / Write Operation
Min
Max
0.1
Units
ms
6. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 30 pF
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
9. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
10. The t
WC
time can be set by the user to allow faster internal writes (max 3 ms) by setting the t
WC
bit from the Status Register. The fast write
mode is recommended for V
CC
> 2.5 V.
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EA2M
Pin Description
Functional Description
SI:
The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO:
The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and EA2M.
CS:
The chip select input pin is used to enable/disable the
EA2M. When CS is high, the SO output is tri−stated (high
impedance) and the device is in Standby Mode (unless an
internal write operation is in progress).
Every
communication session between host and EA2M must be
preceded by a high to low transition and concluded with a
low to high transition of the CS input.
WP:
The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low and the WPEN bit in the Status Register (refer to
Status Register description, later in this Data Sheet) is set to
“1”, writing to the Status Register is disabled.
HOLD:
The HOLD input pin is used to pause transmission
between host and EA2M, without having to retransmit the
entire sequence at a later time. To pause, HOLD must be
taken low and to resume it must be taken back high, with the
SCK input low during both transitions.
The EA2M device supports the Serial Peripheral Interface
(SPI) bus protocol, modes (0,0) and (1,1). The device
contains an 8−bit instruction register. The instruction set and
associated op−codes are listed in Table 7.
Reading data stored in the EA2M is accomplished by
simply providing the READ command and an address.
Writing to the EA2M, in addition to a WRITE command,
address and data, also requires enabling the device for
writing by first setting certain bits in a Status Register, as will
be explained later.
After a high to low transition on the CS input pin, the
EA2M will accept any one of the six instruction op−codes
listed in Table 7 and will ignore all other possible 8−bit
combinations. The communication protocol follows the
timing from Figure 2.
The EA2M features an additional Identification Page (256
bytes) which can be accessed for Read and Write operations
when the IPL bit from the Status Register is set to “1”. The
user can also choose to make the Identification Page
permanent write protected by setting the LIP bit from the
Status Register (LIP=“1”).
Table 7. INSTRUCTION SET
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
Figure 2. Synchronous Data Timing
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EA2M
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1
during an internal write cycle, and reset to 0 when the device
is ready to accept commands. For the host, this bit is read
only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
The TWC (Write Cycle Time) bit is set by the user with
the WRSR command and is volatile. When set to 0, the
device is in a standard write mode with optimum ICC write,
when set to 1 the device is in a fast write mode.
Note: The fast write mode is recommended to be used only
with VCC > 2.5 V.
Table 8. STATUS REGISTER
7
WPEN
6
IPL
5
TWC
4
LIP
The WPEN (Write Protect Enable) bit acts as an enable
for the WP pin. Hardware write protection is enabled when
the WP pin is low and the WPEN bit is 1. This condition
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
The IPL (Identification Page Latch) bit determines
whether the additional Identification Page (IPL = 1) or main
memory array (IPL = 0) can be accessed both for Read and
Write operations. The IPL bit is set by the user with the
WRSR command and is volatile. The IPL bit is
automatically reset after read/write operations. The LIP bit
is set by the user with the WRSR command and is
non-volatile. When set to 1, the Identification Page is
permanently write protected (locked in Read-only mode).
Note: The IPL and LIP bits cannot be set to 1 using the
same WRSR instruction. If the user attempts to set (“1”)
both the IPL and LIP bit in the same time, these bits cannot
be written and therefore they will remain unchanged.
3
BP1
2
BP0
1
WEL
0
RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
BP1
0
0
1
1
BP0
0
1
0
1
Array Address Protected
None
30000h−3FFFFh
20000h−3FFFFh
00000h−3FFFFh
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 10. WRITE PROTECT CONDITIONS
WPEN
0
0
1
1
X
X
WP
X
X
Low
Low
High
High
WEL
0
1
0
1
0
1
Protected Blocks
Protected
Protected
Protected
Protected
Protected
Protected
Unprotected Blocks
Protected
Writable
Protected
Writable
Protected
Writable
Status Register
Protected
Writable
Protected
Protected
Protected
Writable
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